Automatic generation of observers from MARTE/CCSL

Proceedings - IEEE International Symposium on Rapid System Prototyping, RSP

Volumn , Issue , 2012, Pages 86-92

  Mallet, Frédéric ^a  

^a UNIVERSITÉ CÔTE D'AZUR   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC GENERATION; BOUNDEDNESS; CLOCK CONSTRAINTS; GENERIC MECHANISM; HIGH LEVEL SPECIFICATION; MODELING AND ANALYSIS; MODELING CAPABILITIES; MODELING FRAMEWORKS; PROTOTYPE IMPLEMENTATIONS; SYSTEM ON CHIP DESIGN; UML(UNIFIED MODELING LANGUAGE); VERIFICATION TECHNIQUES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; SEMANTICS; UNIFIED MODELING LANGUAGE;

SPECIFICATIONS;

EID: 84873442018     PISSN: 21505500     EISSN: 21505519     Source Type: Conference Proceeding    
DOI: 10.1109/RSP.2012.6380695     Document Type: Conference Paper

References (20)

1. OMG, UML Profile for MARTE, v1.0, Object Management Group, November 2009, formal/2009-11-02.
2. C. André, F. Mallet, and R. de Simone, " Modeling time(s)" in 10th Int. Conf. on Model Driven Engineering Languages and Systems (MODELS '07), ser. LNCS, no. 4735, ACM-IEEE. Nashville, TN, USA: Springer, September 2007, pp. 559-573.
3. C. André, " Syntax and semantics of the Clock Constraint Specification Language (CCSL)," INRIA, Research Report 6925, May 2009. [Online]. Available: http://hal.inria.fr/inria-00384077/
4. C. André, F. Mallet, and J. DeAntoni, " VHDL observers for clock constraint checking," in Industrial Embedded Systems (SIES), 2010 Int. Symp. on. Trento, Italy: IEEE, July 2010, pp. 98-107.
5. A. Benveniste, P. Caspi, S. A. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone, " The synchronous languages 12 years later," Proc. of the IEEE, vol. 91, no. 1, pp. 64-83, 2003.
6. P. Le Guernic, J.-P Talpin, and J.-C. Le Lann, " Polychrony for system design," Journal of Circuits, Systems, and Computers, vol. 12, no. 3, pp. 261-304, 2003.
7. E. A. Lee and A. L. Sangiovanni-Vincentelli, " A framework for comparing models of computation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1217-1229, December 1998.
8. N. Halbwachs, F. Lagnier, and P. Raymond, " Synchronous observers and the verification of reactive systems," in AMAST '93: Proc. of the Third Int. Conf. on Methodology and Software Technology. London, UK: Springer-Verlag, 1994, pp. 83-96.
9. L. Aceto, A. Burgueño, and K. G. Larsen, "Model checking via reachability testing for timed automata," in TACAS, ser. Lecture Notes in Computer Science, B. Steffen, Ed., vol. 1384. Springer, 1998, pp. 263-280. (Pubitemid 128055549)
10. S. Bensalem, M. Bozga, M. Krichen, and S. Tripakis, "Testing conformance of real-time applications by automatic generation of observers," ENTCS, vol. 113, pp. 23-43, 2005. (Pubitemid 40073304)
11. C. André and F. Mallet, " Specification and verification of time requirements with CCSL and esterel," in Languages, Compilers, and Tools for Embedded Systems, C. Kirsch and M. Kandemir, Eds., vol. 44. Irlande Dublin: ACM SIGPLAN/SIGBED, 2009, pp. 167-176. [ Online]. Available: http://hal.inria.fr/inria-00416654/
12. A. Arnold, Finite transition systems - semantics of communicating systems, ser. Int. Series in Computer Science. Prentice Hall, 1994.
13. J. Deantoni and F. Mallet, " Timesquare: Treat your models with logical time," in Tools (50), ser. Lecture Notes in Computer Science, C. A. Furia and S. Nanz, Eds., vol. 7304. Springer, 2012, pp. 34-41.
14. L. P. Carloni, K. L. McMillan, A. Saldanha, and A. L. SangiovanniVincentelli, " A methodology for correct-by-construction latency insensitive design," in Iccad, J. K. White and E. Sentovich, Eds. IEEE, 1999, pp. 309-315.
15. G. Berry and L. Cosserat, " The esterel synchronous programming language and its mathematical semantics," in Seminar on Concurrency, ser. LNCS, S. D. Brookes, A. W. Roscoe, and G. Winskel, Eds., vol. 197. Springer, 1984, pp. 389-448.
16. E. A. Lee, " Modeling concurrent real-time processes using discrete events," Ann. Software Eng., vol. 7, pp. 25-45, 1999.
17. H. Yu, J.-P. Talpin, L. Besnard, T. Gautier, H. Marchand, and P. Le Guernic, " Polychronous controller synthesis from MARTE CCSL timing specifications," in Memocode, S. Singh, B. Jobstmann, M. Kishinevsky, and J. Brandt, Eds. IEEE, 2011, pp. 21-30.
18. L. Yin, F. Mallet, and J. Liu, " Verification of MARTE/CCSL time requirements in Promela/SPINin Iceccs, I. Perseil, K. Breitman, and R. Sterritt, Eds. IEEE Computer Society, 2011, pp. 65-74.
19. R. Gascon, F. Mallet, and J. DeAntoni, " Logical time and temporal logics: Comparing UML MARTE/CCSL and PSL," in Time, C. Combi, M. Leucker, and F. Wolter, Eds. IEEE, 2011, pp. 141-148.
20. " IEEE standard for Property Specification Language (PSL), IEEE std 1850-2005."