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Volumn , Issue , 2011, Pages 141-148

Logical time and temporal logics: Comparing UML MARTE/CCSL and PSL

Author keywords

Automaton based approach; High level design; Language equivalence; Linear temporal logic

Indexed keywords

ANALYSIS METHOD; AUTOMATON BASED APPROACH; CLOCK CONSTRAINTS; ELECTRONIC DESIGN AUTOMATION; ELECTRONIC SYSTEMS; FORMAL NOTATIONS; FORMAL VERIFICATIONS; HIGH-LEVEL DESIGN; INTERMEDIATE REPRESENTATIONS; LANGUAGE EQUIVALENCE; LINEAR TEMPORAL LOGIC; MODELING AND ANALYSIS; PROPERTY SPECIFICATION LANGUAGE; REAL-TIME AND EMBEDDED SYSTEMS; TEMPORAL LOGIC PROPERTIES; UML PROFILES;

EID: 81455142905     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TIME.2011.10     Document Type: Conference Paper
Times cited : (31)

References (12)
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  • 2
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    • VHDL observers for clock constraint checking
    • C. Andrwé, F. Mallet, and J. DeAntoni. VHDL observers for clock constraint checking. In SIES 2010, pages 98-107, 2010.
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  • 5
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    • Safely freezing LTL
    • Springer
    • R. Lazić. Safely freezing LTL. In In FST&TCS'06, pages 381-392. Springer, 2006.
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    • Lazić., R.1
  • 6
    • 70350070603 scopus 로고    scopus 로고
    • Executing AADL models with UML/Marte
    • IEEE Computer Press
    • F. Mallet, C. André, and J. DeAntoni. Executing AADL models with UML/Marte. In ICECCS'09, pages 371-376. IEEE Computer Press, 2009.
    • (2009) ICECCS'09 , pp. 371-376
    • Mallet, F.1    André, C.2    Deantoni, J.3
  • 7
    • 0021470447 scopus 로고
    • Alternating finite automata on ω- words
    • S. Miyano and T. Hayashi. Alternating finite automata on ω- words. TCS, 32(3):321 - 330, 1984.
    • (1984) TCS , vol.32 , Issue.3 , pp. 321-330
    • Miyano, S.1    Hayashi, T.2
  • 8
    • 77955460592 scopus 로고    scopus 로고
    • OMG. Object Management Group, formal/2009-11-02
    • OMG. UML Profile for MARTE, v1.0. Object Management Group, 2009. formal/2009-11-02.
    • (2009) UML Profile for MARTE, v1.0.
  • 9
    • 77949310957 scopus 로고    scopus 로고
    • Generating heterogeneous executable specifications in SystemC from UML/MARTE models
    • P. Peil, J. Medina, H. Posadas, and E. Villar. Generating heterogeneous executable specifications in SystemC from UML/MARTE models. ISSE, 6:65-71, 2010.
    • (2010) ISSE , vol.6 , pp. 65-71
    • Peil, P.1    Medina, J.2    Posadas, H.3    Villar, E.4
  • 11
    • 0022092438 scopus 로고
    • Complexity of propositional linear temporal logics
    • DOI 10.1145/3828.3837
    • A. Sistla and E. Clarke. The complexity of propositional linear temporal logics. JACM, 32(3):733-749, 1985. (Pubitemid 15507395)
    • (1985) Journal of the ACM , vol.32 , Issue.3 , pp. 733-749
    • Sistla, A.P.1    Clarke, E.M.2
  • 12
    • 70350043918 scopus 로고    scopus 로고
    • A co-design approach for embedded system modeling and code generation with UML and MARTE
    • J. Vidal, F. de Lamotte, G. Gogniat, P. Soulard, and J.-P. Diguet. A co-design approach for embedded system modeling and code generation with UML and MARTE. In DATE, pages 226-231, 2009.
    • (2009) DATE , pp. 226-231
    • Vidal, J.1    De Lamotte, F.2    Gogniat, G.3    Soulard, P.4    Diguet, J.-P.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.