Polychronous controller synthesis from MARTE CCSL timing specifications

9th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011

Volumn , Issue , 2011, Pages 21-30

  Yu, Huafeng ^a   Talpin, Jean Pierre ^a   Besnard, Loic ^a   Gautier, Thierry ^a   Marchand, Hervé ^a   Le Guernic, Paul ^a  

^a INRIA   (France)

Author keywords

CCSL; controller synthesis; GALS; MARTE; Polychrony

Indexed keywords

CCSL; CONTROLLER SYNTHESIS; GALS; MARTE; POLYCHRONY;

EMBEDDED SYSTEMS; FORMAL METHODS; MODEL CHECKING; REAL TIME SYSTEMS; SPECIFICATION LANGUAGES; SPECIFICATIONS; TIMING CIRCUITS;

CONTROLLERS;

EID: 80052105111     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2011.5970507     Document Type: Conference Paper

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