DFM metrics for standard cells

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 491-496

  Aitken, Robert ^a  

^a ARM Phys IP Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL DESIGN; DESIGN-FOR-MANUFACTURABILITY; PROCESS GEOMETRIES; STANDARD CELL;

MACHINE DESIGN;

EID: 84871960365     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.50     Document Type: Conference Paper

References (9)

1. H.T. Heineken, J. Khare, and M. d'Abreu, "Manufacturability Analysis of Standard Cell Libraries", Proc Custom Int. Circ. Conf, pp. 321-324, May 1998.
2. C. Guardiani, N. Dragone, and P. McNamara, "Proactive Design for Manufacturing (DFM) for Nanometer SoC Designs", Proc Custom Int. Circ. Conf, pp. 309-316, 2004.
3. A. Nardi and A. Sangiovanni-Vincentelli, "Synthesis for Manufacturability: a Sanity Check", Proc. Des. Aut. & Test Europe, pp. 796-801, February 2004.
4. C. Bittlestone et al, "Architecting ASIC Libraries and Flows in Nanometer Era", Proc. Design Automation Conf., pp. 776-781, June 2003.
5. L. Pileggi et al, "Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off ", Proc. Design Automation Conf., pp., 782-787, 2003.
6. P. Li, P. Nag, and W. Maly, "Cost Based Tradeoff Analysis of Standard Cell Designs", Proc. SLIP 2000, pp. 129-135, 2000.
7. F. J. Ferguson and J. P. Shen, "Extraction and Simulation of Realistic Faults Using Inductive Fault Analysis", Proc. International Test Conference, pp. 475-484, 1988.
8. R. Daasch et al, "Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data", Proc. International Test Conference, pp. 92-100, 2001.
9. W. Pleskacz, C. Ouyang, and W. Maly, "A DRC Based Algorithm for Extraction of Critical Areas for Opens in Large VLSI Circuits", IEEE Trans. CAD, Vol. 18, No. 2, Feb. 1999.