Cost based tradeoff analysis of standard cell designs

International Workshop on System-Level Interconnect Prediction (SLIP 2000)

Volumn , Issue , 2000, Pages 129-135

  Li, Peng ^a   Nag, Pranab K ^a   Maly, Wojciech ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

A posteriori wire length estimation; Die size estimation; Yield and cost prediction

Indexed keywords

CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; ELECTRIC WIRE; ESTIMATION; LAYERED MANUFACTURING; MICROPROCESSOR CHIPS;

CELL DESIGN;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034592627     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/333032.333043     Document Type: Conference Paper

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