UNIVERCM: The UNIversal VERsatile computational model for heterogeneous system integration

IEEE Transactions on Computers

Volumn 62, Issue 2, 2013, Pages 225-241

  Di Guglielmo, Luigi ^a   Fummi, Franco ^a   Pravadelli, Graziano ^a   Stefanni, Francesco ^a   Vinco, Sara ^a  

^a UNIVERSITY OF VERONA   (Italy)

Author keywords

electronic design automation; Formal specifications; modeling; multiprocessor; simulation

Indexed keywords

COMPUTATION THEORY; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; ELECTRONIC DESIGN AUTOMATION; EMBEDDED SYSTEMS; FORMAL SPECIFICATION; MODELS; MULTIPROCESSING SYSTEMS; SEMANTICS;

COMPONENT BASED DESIGN; HETEROGENEOUS CHIP MULTIPROCESSOR; HETEROGENEOUS COMPONENT; HETEROGENEOUS SYSTEMS; INTERMEDIATE FORMATS; MODERN EMBEDDED SYSTEMS; MULTIPROCESSOR; SIMULATION;

LOGIC DESIGN;

EID: 84871668273     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2012.156     Document Type: Article

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