HArtes: Hardware-software codesign for heterogeneous multicore platforms

IEEE Micro

Volumn 30, Issue 5, 2010, Pages 88-97

  Bertels, Koen ^a   Sima, Vlad Mihai ^a   Yankova, Yana ^a   Kuzmanov, Georgi ^a   Luk, Wayne ^b   Coutinho, Gabriel ^b   Ferrandi, Fabrizio ^c   Pilato, Christian ^c   Lattuada, Marco ^c   Sciuto, Donatella ^c   Michelotti, Andrea ^d  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

^c POLITECNICO DI MILANO   (Italy)

^d Atmel Roma ^*  (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

HARDWARE COMPONENTS; HARDWARE CONFIGURATIONS; HARDWARE SOFTWARE CODESIGN; HETEROGENEOUS MULTICORE; SEMI-AUTOMATICS;

EID: 78649497246     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2010.91     Document Type: Article

References (7)

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2. F. Ferrandi et al., "Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs", Proc. Int'l Embedded Systems Symp. (IESS 07), IFIP 231, Springer, 2007, pp. 179-192.
3. F. Ferrandi et al., "Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions", Proc. 7th ACM/IEEE Int'l Conf. Formal Methods and Models for Codesign (Memocode 09), IEEE Press, 2009, pp. 131-140.
4. W. Luk et al., "A High-Level Compilation Toolchain for Heterogeneous Systems", Proc. IEEE Int'l SoC Conf. (SOCC 09), IEEE Press, 2009, pp. 9-18.
5. Y. M. Lam et al., "Mapping and Scheduling with Task Clustering for Heterogeneous Computing Systems", Proc. Int'l Conf. Field Programmable Logic and Applications (FPL 08), IEEE Press, 2008, pp. 275-280.
6. Y. D. Yankova et al., "DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator", Proc. Int'l Conf. Field Programmable Logic and Applications (FPL 07), IEEE Press, 2007, pp. 697-701.
7. V.-M. Sima and K. Bertels, "Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform", Proc. Int'l Conf. Reconfigurable Computing and FPGAs, IEEE CS Press, 2009, pp. 71-76.