Scenario-oriented design for single-chip heterogeneous multiprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 8, 2006, Pages 868-880

  Paul, JoAnn M ^a,b   Thomas, Donald E ^a,c   Bobrek, Alex ^a,c  

^a IEEE   (United States)

^b State University   (United States)

^c CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Benchmarking; Design methodology; Heterogeneous multiprocessor; Modeling; Scenario oriented design; System on chip (SOC)

Indexed keywords

DESIGN METHODOLOGY; HETEROGENEOUS MULTIPROCESSOR; SCENARIO-ORIENTED DESIGN; SYSTEM-ON-CHIP (SOC);

BENCHMARKING; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; MICROPROCESSOR CHIPS; REAL TIME SYSTEMS;

MULTIPROCESSING SYSTEMS;

EID: 33747415832     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.878474     Document Type: Article

References (17)

1. Commun. ACM, vol. 46, Special Issue on Ubiquitous Computing, no. 12, Dec. 2002.
2. T. Austin, D. Blaauw, S. Mahlke, T. Mudge, C. Chakrabarti, and W. Wolf, "Mobile supercomputers," IEEE Comput., vol. 37, no. 5, pp. 81-83, May 2004.
3. W. Wolf, "How many system architectures?," IEEE Comput., vol. 36, no. 3, pp. 93-95, Mar. 2003.
4. International Technology Roadmap for Semiconductors 2003 [Online]. Available: http://public.itrs.net/
5. J. Paul, "Programmers' views of SoCs," in Proc. CODES-ISSS, 2003, pp. 156-181.
6. G. DeMicheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
7. N. Sherwani, Algorithms for VLSI Physical Design Automation. Norwell, MA: Kluwer, 1993.
8. K. Keutzer, "System-level design: Orthogonalization of concerns and platform-based design," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
9. T. Austin, E. Larson, and D. Ernst, "Simplescalar: An infrastructure for computer system modeling," IEEE Comput., vol. 35, no. 2, pp. 59-67, Feb. 2002.
10. R. Giladi and N. Ahitav, "SPEC as a performance evaluation measure," IEEE Comput., vol. 28, no. 8, pp. 33-42, Aug. 1995.
11. M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, and R. Brown, "MiBench: A free, commercially representative embedded benchmark suite," in Proc. 4th Workshop Workload Characterization, 2001, pp. 1-12.
12. C. Lee, M. Potkonjak, and W. Mangione-Smith, "MediaBench: A tool for evaluating and synthesizing multimedia and communications systems," in Proc. ISCA, 1997, pp. 330-335.
13. B. Selic, "Turning clockwise: Using UML in the real-time-domain, " Commun. ACM, pp. 46-54, Oct. 1999.
14. M. Nikitovic and M. Brorsson, "A multiprogrammed workload model for energy and performance estimation of adaptive chip-multiprocessors," in Proc. Parallel Distrib. Process. Symp., Apr. 2004, pp. 251-251.
15. F. Karim, A. Mellan, B. Stramm, T. Abdelrahman, and U. Aydonat, "The hyperprocessor: A template architecture for embedded multimedia applications," in Proc. WASP, 2003, pp. 66-73.
16. K. Lahiri, "LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs," in Proc. DAC, 2001, pp. 15-20.
17. A. Bobrek, J. Pieper, J. Nelson, J. Paul, and D. Thomas, "Modeling shared resource contention using a hybrid simulation/analytical approach," in Proc. DATE, 2004, pp. 1144-1149.