From OpenCL to high-performance hardware on FPGAs

Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Volumn , Issue , 2012, Pages 531-534

  Czajkowski, Tomasz S ^a   Aydonat, Utku ^a   Denisenko, Dmitry ^a   Freeman, John ^a   Kinsner, Michael ^a   Neto, David ^a   Wong, Jason ^a   Yiannacouras, Peter ^a   Singh, Deshanand P ^a  

^a ALTERA CORPORATION   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; COMPUTING PARADIGM; HIGH-PERFORMANCE COMPUTING APPLICATIONS; HIGH-PERFORMANCE HARDWARE; VERILOG HDL;

COMPUTER SOFTWARE SELECTION AND EVALUATION; DESIGN; HARDWARE;

BENCHMARKING;

EID: 84870653601     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2012.6339272     Document Type: Conference Paper

References (13)

1. M. Leeser, S. Corid, E. Miller, H. Yu, and M. Trepanier, "Parallel-beam backprojection: An FPGA implementation optimized for medical imaging," Journal of VLSI Signal Processing, vol. 39, no. 3, pp. 295-311, 2005.
2. H. Guo, L. Su, Y. Wang, and Z. Long, "FPGA-accelerated molecular dynamics simulations system," Inter. Conf. on Embedded Computing, pp. 360-365, 2009.
3. Khronos OpenCL Working Group, The OpenCL Specification, version 1.1.48, June 2009. [Online]. Available: http://www.khronos.org/registry/ cl/specs/opencl-1.0.pdf
4. LLVM, The LLVM Compiler Infrastructure Project, 2010. [Online]. Available: http://www.llvm.org
5. M. Owaida, N. Bellas, K. Daloukas, and C. Antonopoulos, "Synthesis of platform architectures from OpenCL programs," in FCCM, may 2011, pp. 186 -193.
6. P. O. Jääskeläinen, C. S. de La Lama, P. Huerta, and J. H. Takala, "OpenCL-based design methodology for applicationspecific processors," in SAMOS X: Embedded Computer Systems: Architectures, Modeling, and Simulation, July 2010.
7. A. Papakonstantinou, G. Karthik, J. A. Stratton, D. Chen, J. Cong, and W.-M. W. Hwu, "FCUDA: Enabling efficient compilation of cuda kernels onto fpgas," in Proc. of the 7th Symp. on ASPs, jul 2009, pp. 35-42.
8. R. Cytron, J. Ferrante, B. K. Rosen, M. N.Wegman, and F. K. Zadeck, "Efficiently computing static single assignment form and the control dependence graph," ACM Trans. on Prog. Lang. and Systems, vol. 13, no. 4, pp. 451-490, Oct 1991.
9. J. Cortadella, M. Kishinevsky, and B. Grundmann, "Synthesis of synchronous elastic architectures," in Design Automation Conference, July 2006, pp. 657-662.
10. J. Cortadella and M. Kishinevsky, "Synchronous elastic circuits with early evaluation and token counterflow," in Design Automation Conference, June 2007, pp. 416-419.
11. J. Cong and Z. Zhang, "Activity estimation for field-programmable gate arrays," in IEEE/ACM Design Automation Conference, 2006, pp. 433-438.
12. N. A. Woods, "FPGA acceleration of european options pricing," XtremeData Inc. - White Paper, 2008.
13. V. Kumar, S. Joshi, S. Patkar, and H. Narayanan, "Fpga based high performance double-precision matrix multiplication," International Journal of Parallel Programming, vol. 38, pp. 322-338, 2010.