Parallel-beam backprojection: An FPGA implementation optimized for medical imaging

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 39, Issue 3, 2005, Pages 295-311

  Leeser, Miriam ^a   Coric, Srdjan ^a   Miller, Eric ^a   Yu, Haiqian ^a   Trepanier, Marc ^b  

^a NORTHEASTERN UNIVERSITY   (United States)

^b Mercury Computer Systems Inc   (United States)

Author keywords

Backprojection; Fixed point arithmetic; FPGA; Medical imaging; Tomography

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; COMPUTERIZED TOMOGRAPHY; DATA PROCESSING; ERROR ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE COMPRESSION; IMAGE QUALITY; IMAGE RECONSTRUCTION; IMAGE SENSORS; OPTIMIZATION;

BACKPROJECTION; FIXED POINT ARITHMETIC; HARDWARE ACCELERATION; MEDICAL SENSORS;

MEDICAL IMAGING;

EID: 14844340234     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11265-005-4846-5     Document Type: Article

References (16)

1. A.C. Kak and M. Slaney, Principles of Computerized Tomographic Imaging, New York: IEEE Press, 1988.
2. M.A. Wu, "ASIC Applications in Computed Tomography Systems, " in Proceedings of Fourth Annual IEEE International ASIC Conference and Exhibit, Rochester, NY, USA, 1991, pp. P1-3/1-4.
3. I. Agi, P.J. Hurst, and K.W. Current, "An Image Processing IC for Backprojection and Spatial Histogramming in a Pipelined Array, " IEEE Journal of Solid-state Circuits, vol. 28, no. 3, 1993, pp. 210-221.
4. I. Agi, P.J. Hurst, and K.W. Current, "A VLSI Architecture for High-Speed Image Reconstruction: Considerations for a Fixed-Point Architecture, " in Proceedings of SPIE, Parallel Architectures for Image Processing, vol. 1246, 1990, pp. 11-24.
5. Stephen G. Azevedo, Brian K. Cabral, and J. Foran, "Tomographic Image Reconstruction and Rendering with Texture-Mapping Hardware, " in Proceedings of Mathematical Methods in Medical Imaging III, SPIE, vol. 2299, 1994, pp. 280-289.
6. C.B. Luiz Maltar, Felipe M.G. Franca, V.C. Alves, and C.L. Amorim, "Reconfigurable Hardware for Tomographic Processing, " in Proceedings of the XI Brazilian Symposium on Integrated Circuit Design, Rio de Janeiro/RJ: IEEE Computer Society Press, 1998, pp. 19-24.
7. 2N) Filtered Backprojection Reconstruction Algorithm for Tomography, " IEEE Transactions on Image Processing, vol. 9, no. 10, 2000, pp. 1760-1773.
8. Chen, Chung-Ming, Cho, Zang-Hee, and Wang, Cheng-Yi, "A Fast Implementation of the Incremental Backprojection Algorithms for Parallel Beam Geometries, " IEEE Transactions on Nuclear Science, vol. 43, no. 6, 1996, pp. 3328-3334.
9. C.B. Luiz Maltar, F.M.G. Franca, V.C. Alves, and C.L. Amorim, "An FPGA-Based Fan Beam Image Reconstruction Module", in Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, April 1999, pp. 331-332.
10. R. Yu, R. Ning, and B. Chen, "High Speed Cone Beam Reconstruction on PC, " SPIE Medical Imaging 2001, San Diego, CA, Feb. 17-22, 2001, pp. 964-973.
11. I. Goddard and M. Trepanier, "High-Speed Cone-Beam Reconstruction: An Embedded Systems Approach", SPIE Medical Imaging 2002, San Diego, CA, Feb 24-26, 2002, pp. 483-491.
12. J. Bins, B. Draper, W. Bohm, and W. Najjar, "Precision vs. Error in JPEG Compression, " Parrallel and Distributed Methods for Image Processing III (SPIE), Denver CO, Jul 22, 1999, pp. 76-87.
13. S. Coric, M. Leeser, E. Miller, and M. Trepanier, "Parallel-Beam Backprojection: an FPGA Implementation Optimized for Medical Imaging, " in Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA02), February, 2002, pp. 217-226.
14. P.M. Joseph, "An improved algorithm for reprojecting rays through pixel images, " IEEE Transactions on Medical Imaging, vol. MI-1, no. 3, Nov 1982, pp. 192-196.
15. http://www.nlm.nih.gov/research/visible/fresh@ct.html, last accessed Nov 14, 2002
16. Z. Guo, W. Najjar, F. Vahid, and K. Vissers, "A Quantitative Analysis of the Speedup Factors of FPGAs over processors, " in Twelfth ACM International Symposium on Field-Programmable Gate Arrays (FPGA04), February, 2004, pp. 162-170.