FPGA based high performance double-precision matrix multiplication

International Journal of Parallel Programming

Volumn 38, Issue 3-4, 2010, Pages 322-338

  Kumar, Vinay B Y ^a   Joshi, Siddharth ^a   Patkar, Sachin B ^a   Narayanan, H ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

FPGA implementation; High performance computing; Matrix multiplication; Memory bandwidth trade off; Rank 1 scheme; Scalability

Indexed keywords

FPGA IMPLEMENTATIONS; HIGH PERFORMANCE COMPUTING; MATRIX MULTIPLICATION; MEMORY BANDWIDTHS; RANK-1 SCHEME;

BANDWIDTH; COMMERCE; MATRIX ALGEBRA; OPTIMIZATION; SCALABILITY;

DESIGN;

EID: 77955921190     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10766-010-0131-8     Document Type: Conference Paper

References (12)

1. Baxter, R., Booth, S., Bull, M., Cawood, G., Perry, J., Parsons,M., Simpson, A., Trew, A., McCormick, A., Smart, G., Smart, R., Cantle, A., Chamberlain, R., Genest, G.: Maxwell-a 64 fpga supercomputer. In: AHS '07: Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems, pp. 287-294. IEEE Computer Society, Washington, DC, USA (2007)
2. Baxter, R., Booth, S., Bull, M., Cawood, G., Perry, J., Parsons, M., Simpson, A., Trew, A., McCormick, A., Smart, G., Smart, R., Cantle, A., Chamberlain, R., Genest, G.: The fpga high-performance computing alliance parallel toolkit. In: AHS '07: Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems, pp. 301-310. IEEE Computer Society, Washington, DC, USA (2007)
3. Underwood, K.D., Hemmert, K.S.: Closing the gap: Cpu and fpga trends in sustainable floating-point blas performance. In: FCCM, pp. 219-228. IEEE Computer Society (2004)
4. Zhuo, L., Prasanna, V.K.: High-performance designs for linear algebra operations on reconfigurable hardware. IEEE Trans. Comput. 57(8), 1057-1071 (2008)
5. Craven, S., Athanas, P.: Examining the viability of fpga supercomputing. EURASIP J. Embed. Syst. 2007(1), 13-13 (2007)
6. Kumar, V.B.Y., Joshi, S., Patkar, S.B., Narayanan, H.: Fpga based high performance double-precision matrix multiplication. In: VLSID '09: Proceedings of the 2009 22nd International Conference on VLSI Design, pp. 341-346. IEEE Computer Society, Washington, DC, USA (2009)
7. Zhuo, L., Prasanna, V.K.: Scalable and modular algorithms for floating-point matrix multiplication on reconfigurable computing systems. IEEE Trans. Parallel Distrib. Syst. 18(4), 433-448 (2007)
8. Goto, K., van de Geijn, R.: High performance implementation of the level-3 BLAS, accepted 28 Oct 2007
9. Dou, Y., Vassiliadis, S., Kuzmanov, G.K., Gaydadjiev, G.N.: 64-bit floating-point fpga matrix multiplication. In: FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-Programmable Gate Arrays, pp. 86-95. ACM, New York, USA (2005)
10. Zhuo, L., Prasanna, V.K.: Scalable and modular algorithms for floating-point matrix multiplication on fpgas. IPDPS 01, 92 (2004)
11. Xilinx Virtex-5 family User Guide
12. Kuzmanov, G., van Oijen, W.: Floating-point matrix multiplication in a polymorphic processor. In: International Conference on Field Programmable Technology (ICFPT), Dec 2007, pp. 249-252