-
1
-
-
84948696213
-
-
S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani, A network on chip architecture and design methodology, 2002, pp. 105-112, http://dx.doi.org/10.1109/ISVLSI.2002.1016885.
-
(2002)
A Network on Chip Architecture and Design Methodology
, pp. 105-112
-
-
Kumar, S.1
Jantsch, A.2
Soininen, J.P.3
Forsell, M.4
Millberg, M.5
Oberg, J.6
Tiensyrja, K.7
Hemani, A.8
-
2
-
-
0036949388
-
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
-
C. Kim, D. Burger, and S.W. Keckler An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches SIGPLAN Not. 37 10 2002 211 222 http://dx.doi.org/10.1145/605432.605420
-
(2002)
SIGPLAN Not.
, vol.37
, Issue.10
, pp. 211-222
-
-
Kim, C.1
Burger, D.2
Keckler, S.W.3
-
3
-
-
60649105359
-
A quantitative study of the on-chip network and memory hierarchy design for many-core processor
-
IEEE Computer Society Washington, DC, USA
-
X. Wang, G. Gan, J. Manzano, D. Fan, and S. Guo A quantitative study of the on-chip network and memory hierarchy design for many-core processor Proceedings of the 2008 14th IEEE International Conference on Parallel and Distributed Systems 2008 IEEE Computer Society Washington, DC, USA 689 696 http://dx.doi.org/10.1109/ICPADS.2008.18
-
(2008)
Proceedings of the 2008 14th IEEE International Conference on Parallel and Distributed Systems
, pp. 689-696
-
-
Wang, X.1
Gan, G.2
Manzano, J.3
Fan, D.4
Guo, S.5
-
4
-
-
34548050337
-
Fair queuing memory systems
-
IEEE Computer Society Washington, DC, USA
-
K.J. Nesbit, N. Aggarwal, J. Laudon, and J.E. Smith Fair queuing memory systems MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture 2006 IEEE Computer Society Washington, DC, USA 208 222 http://dx.doi.org/10.1109/MICRO.2006.24
-
(2006)
MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
, pp. 208-222
-
-
Nesbit, K.J.1
Aggarwal, N.2
Laudon, J.3
Smith, J.E.4
-
5
-
-
0031237070
-
Virtual-address caches. Part 1: Problems and solutions in uniprocessors
-
M. Cekleov, and M. Dubois Virtual-address caches. Part 1: Problems and solutions in uniprocessors IEEE Micro 17 5 1997 64 71 http://dx.doi.org/10.1109/ 40.621215
-
(1997)
IEEE Micro
, vol.17
, Issue.5
, pp. 64-71
-
-
Cekleov, M.1
Dubois, M.2
-
6
-
-
0031274147
-
Virtual-address caches. 2. Multiprocessor issues
-
M. Cekleov, and M. Dubois Virtual-address caches. 2. Multiprocessor issues IEEE Micro 17 6 1997 69 74 http://dx.doi.org/10.1109/40.641599
-
(1997)
IEEE Micro
, vol.17
, Issue.6
, pp. 69-74
-
-
Cekleov, M.1
Dubois, M.2
-
7
-
-
74549189505
-
Memory management thread for heap allocation intensive sequential applications
-
ACM New York, NY, USA
-
D. Tiwari, S. Lee, J. Tuck, and Y. Solihin Memory management thread for heap allocation intensive sequential applications Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA'09 2009 ACM New York, NY, USA 35 42 http://dx.doi.org/10. 1145/1621960.1621967
-
(2009)
Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA'09
, pp. 35-42
-
-
Tiwari, D.1
Lee, S.2
Tuck, J.3
Solihin, Y.4
-
10
-
-
0029194459
-
The SPLASH-2 programs: Characterization and methodological considerations
-
J.P. Singh, A. Gupta, M. Ohara, E. Torrie, S.C. Woo, The SPLASH-2 programs: Characterization and methodological considerations, in: International Symposium on Computer Architecture, 1995, pp. 24-36, http://dx.doi.org/10.1109/ ISCA.1995.524546.
-
(1995)
International Symposium on Computer Architecture
, pp. 24-36
-
-
Singh, J.P.1
Gupta, A.2
Ohara, M.3
Torrie, E.4
Woo, S.C.5
-
11
-
-
45149087010
-
-
M. Monchiero, G. Palermo, C. Silvano, O. Villa, Exploration of distributed shared memory architectures for NoC-based multiprocessors, 2006, pp. 144-151, http://dx.doi.org/10.1109/ICSAMOS.2006.300821.
-
(2006)
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors
, pp. 144-151
-
-
Monchiero, M.1
Palermo, G.2
Silvano, C.3
Villa, O.4
-
12
-
-
33749395124
-
Microarchitecture optimizations for exploiting memory-level parallelism
-
Y. Chou, B. Fahs, and S. Abraham Microarchitecture optimizations for exploiting memory-level parallelism SIGARCH Comput. Archit. News 32 2 2004 http://portal.acm.org/citation.cfm?id=1006708
-
(2004)
SIGARCH Comput. Archit. News
, vol.32
, Issue.2
-
-
Chou, Y.1
Fahs, B.2
Abraham, S.3
-
14
-
-
70450231944
-
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
-
ACM New York, NY, USA
-
S. Hong, and H. Kim An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness ISCA'09: Proceedings of the 36th Annual International Symposium on Computer Architecture 2009 ACM New York, NY, USA 152 163 http://dx.doi.org/10.1145/1555754.1555775
-
(2009)
ISCA'09: Proceedings of the 36th Annual International Symposium on Computer Architecture
, pp. 152-163
-
-
Hong, S.1
Kim, H.2
-
15
-
-
70450285523
-
Achieving predictable performance through better memory controller placement in many-core CMPs
-
ACM New York, NY, USA
-
D. Abts, N.D. Enright Jerger, J. Kim, D. Gibson, and M.H. Lipasti Achieving predictable performance through better memory controller placement in many-core CMPs ISCA'09: Proceedings of the 36th Annual International Symposium on Computer Architecture 2009 ACM New York, NY, USA 451 461 http://dx.doi.org/ 10.1145/1555754.1555810
-
(2009)
ISCA'09: Proceedings of the 36th Annual International Symposium on Computer Architecture
, pp. 451-461
-
-
Abts, D.1
Enright Jerger, N.D.2
Kim, J.3
Gibson, D.4
Lipasti, M.H.5
|