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Volumn 79, Issue 2, 2013, Pages 175-186

Regional cache organization for NoC based many-core processors

Author keywords

Cache organization; Network on chip; On chip communication

Indexed keywords

CACHE MEMORY; MEMORY MANAGEMENT UNITS; PHYSICAL ADDRESSES; SERVERS; TRAFFIC CONGESTION;

EID: 84870301615     PISSN: 00220000     EISSN: 10902724     Source Type: Journal    
DOI: 10.1016/j.jcss.2012.05.002     Document Type: Article
Times cited : (7)

References (15)
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    • An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
    • C. Kim, D. Burger, and S.W. Keckler An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches SIGPLAN Not. 37 10 2002 211 222 http://dx.doi.org/10.1145/605432.605420
    • (2002) SIGPLAN Not. , vol.37 , Issue.10 , pp. 211-222
    • Kim, C.1    Burger, D.2    Keckler, S.W.3
  • 5
    • 0031237070 scopus 로고    scopus 로고
    • Virtual-address caches. Part 1: Problems and solutions in uniprocessors
    • M. Cekleov, and M. Dubois Virtual-address caches. Part 1: Problems and solutions in uniprocessors IEEE Micro 17 5 1997 64 71 http://dx.doi.org/10.1109/ 40.621215
    • (1997) IEEE Micro , vol.17 , Issue.5 , pp. 64-71
    • Cekleov, M.1    Dubois, M.2
  • 6
    • 0031274147 scopus 로고    scopus 로고
    • Virtual-address caches. 2. Multiprocessor issues
    • M. Cekleov, and M. Dubois Virtual-address caches. 2. Multiprocessor issues IEEE Micro 17 6 1997 69 74 http://dx.doi.org/10.1109/40.641599
    • (1997) IEEE Micro , vol.17 , Issue.6 , pp. 69-74
    • Cekleov, M.1    Dubois, M.2
  • 12
    • 33749395124 scopus 로고    scopus 로고
    • Microarchitecture optimizations for exploiting memory-level parallelism
    • Y. Chou, B. Fahs, and S. Abraham Microarchitecture optimizations for exploiting memory-level parallelism SIGARCH Comput. Archit. News 32 2 2004 http://portal.acm.org/citation.cfm?id=1006708
    • (2004) SIGARCH Comput. Archit. News , vol.32 , Issue.2
    • Chou, Y.1    Fahs, B.2    Abraham, S.3
  • 13
  • 14
    • 70450231944 scopus 로고    scopus 로고
    • An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
    • ACM New York, NY, USA
    • S. Hong, and H. Kim An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness ISCA'09: Proceedings of the 36th Annual International Symposium on Computer Architecture 2009 ACM New York, NY, USA 152 163 http://dx.doi.org/10.1145/1555754.1555775
    • (2009) ISCA'09: Proceedings of the 36th Annual International Symposium on Computer Architecture , pp. 152-163
    • Hong, S.1    Kim, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.