22-nm fully-depleted tri-gate CMOS transistors

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2012, Pages

  Auth, Chris ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BULK SILICON; CHANNEL STRAIN; CMOS TRANSISTORS; DRIVE CURRENTS; FULLY DEPLETED; HIGH YIELD; HIGH-VOLUME MANUFACTURING; LOW VOLTAGE OPERATION; METAL-GATE; SELF-ALIGNED; SRAM CELL; SUBTHRESHOLD SLOPE; TECHNOLOGY NODES; THIRD GENERATION; TRI-GATE TRANSISTORS; TRIGATE;

INTEGRATED CIRCUITS;

TRANSISTORS;

EID: 84869446493     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2012.6330657     Document Type: Conference Paper

References (12)

1. T. Ghani et al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," in IEEE Int. Electron Device Meeting Tech. Dig., Washington, DC, pp. 978-980, Dec. 2003.
2. K. Mistry et al., "A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," in IEEE Int. Electron Device Meeting Tech. Dig., Washington, DC, pp. 247-250, Dec. 2007.
3. D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A fully depleted lean-channel transistor (DELTA) - a novel vertical ultra thin SOI MOSFET," in IEEE Int. Electron Device Meeting Tech. Dig., Washington, DC, pp. 833-836, Dec. 1989.
4. X. Huang et al., "Sub 50-nm FinFET: PMOS," in IEEE Int. Electron Device Meeting Tech. Dig., Washington, DC, p. 67-70, Dec. 1999.
5. R. Chau et al., "Advanced depleted-substrate transistors: single-gate, double-gate and tri-gate," in Extended Abstracts of Int. Conf. On Solid-State Devices and Materials, Nagoya, Japan, pp. 68-69, Sep. 2002.
6. A. Dixit et al., "Analysis of the parasitic S/D resistance in multiple-gate FETs," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1132-1140, Jun. 2005.
7. P. Packan et al., "High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors," in IEEE Int. Electron Device Meeting Tech. Dig., Washington, DC, pp. 659-662, Dec. 2009.
8. C. Auth et al., "45nm high-k + metal gate strain-enhanced transistors," in IEEE Symp. VLSI Technology Dig. Tech. Papers, Honolulu, HI, pp. 128-129, Jun. 2008.
9. M. H. Na, E. J. Nowak, W. Haensch, and J. Cai, "The effective drive current in CMOS inverters," in IEEE Int. Electron Device Meeting Tech. Dig., San Francisco, CA, pp. 121-124, Dec. 2002.
10. E. Karl et al., "A 4.6ghZ 162Mb SRAM design in 22nm trigate CMOS technology with integrated active Vmin-enhncing assist circuitry," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, pp. 230-232, Feb. 2012.
11. Y. Wang et al., "A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-k metal-gate CMOS with integrated power management," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, pp.456-457, Feb. 2009.
12. S. Damaraju et al., "A 22nm IA multi-CPU and GPU System-on-Chip," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, pp. 56-57, Feb. 2012.