Timed model checking with abstractions: Towards worst-case response time analysis in resource-sharing manycore systems

EMSOFT'12 - Proceedings of the 10th ACM International Conference on Embedded Software 2012, Co-located with ESWEEK

Volumn , Issue , 2012, Pages 63-72

  Giannopoulou, Georgia ^a   Lampka, Kai ^b   Stoimenov, Nikolay ^a   Thiele, Lothar ^a  

^a ETH ZURICH   (Switzerland)

^b UPPSALA UNIVERSITY   (Sweden)

Author keywords

Multi core systems; Resource contention; Worst case response time analysis

Indexed keywords

ANALYTIC METHOD; BENCHMARK APPLICATIONS; BUS ARBITRATION; COMPUTATION TIME; EMBEDDED REAL TIME SYSTEMS; FLEXRAY; MANY-CORE; MODEL COMPLEXES; MODELING AND ANALYSIS; MULTI-CORE SYSTEMS; MULTICORE ARCHITECTURES; PARALLEL EXECUTIONS; PROCESSING CORE; REAL-TIME TASKS; REAL-WORLD APPLICATION; RESOURCE ACCESS; RESOURCE CONTENTION; RESOURCE SHARING; SHARED RESOURCES; TIMED AUTOMATA; TIMED AUTOMATA MODELS; TIMED MODEL CHECKING; TIMING ANALYSIS; WORST CASE RESPONSE TIME;

ABSTRACTING; AUTOMATA THEORY; AUTOMOTIVE INDUSTRY; EMBEDDED SOFTWARE; MODEL CHECKING; REAL TIME SYSTEMS; SCALABILITY; SOFTWARE ARCHITECTURE;

RESPONSE TIME (COMPUTER SYSTEMS);

EID: 84869071944     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2380356.2380372     Document Type: Conference Paper

References (26)

1. AutoSAR. Release 4.0. http://www.autosar.org.
2. EEMBC 1.1 Embedded Benchmark Suite. http://www.eembc.org/benchmark/ automotive-sl.php.
3. European commission's 7th framework programme: Design for predictability and efficiency. www.predator-project.eu.
4. Flexray communications system protocol specification, version 2.1, revision a. http://www.flexray.com/.
5. R. Alur and D. L. Dill. Automata For Modeling Real-Time Systems. In Automata, Languages and Programming, pages 322-335. Springer, 1990.
6. G. Behrmann, A. David, and K. G. Larsen. A tutorial on uppaal. In Formal Methods for the Design of Real-Time Systems, pages 200-236, 2004.
7. D. B. Chokshi and P. Bhaduri. Performance analysis of flexray-based systems using real-time calculus, revisited. In ACM Symposium on Applied Computing, pages 351-356, 2010.
8. A. Ferrari, M. Di Natale, G. Gentile, G. Reggiani, and P. Gai. Time and memory tradeoffs in the implementation of AUTOSAR components. In Design, Automation, Test in Europe Conference, pages 864 -869, 2009.
9. G. Giannopoulou, N. Stoimenov, A. Schranzhofer, and L. Thiele. Derivation of access request arrival curves for dedicated superblock sequences. TIK-rep. 347, Computer Engineering & Networks Laboratory, ETH Zurich, 2012.
10. A. Gustavsson, A. Ermedahl, B. Lisper, and P. Pettersson. Towards WCET Analysis of Multicore Architectures Using UPPAAL. In Workshop on Worst-Case Execution Time Analysis, pages 101-112, 2010.
11. R. Henia, A. Hamann, M. Jersak, R. Racu, K. Richter, and R. Ernst. System Level Performance Analysis - The SymTA/S Approach. Computers and Digital Techniques, 152(2):148-166, 2005.
12. K. Lampka, S. Perathoner, and L. Thiele. Analytic real-time analysis and timed automata: A hybrid methodology for the performance analysis of embedded real-time systems. Design Automation for Embedded Systems, 14(3):193-227, 2010.
13. K. G. Larsen, C. Weise, W. Yi, and J. Pearson. Clock difference diagrams. Nordic Journal of Computing, 6(3):271-198, 1999.
14. M. Lv, W. Yi, N. Guan, and G. Yu. Combining abstract interpretation with model checking for timing analysis of multicore software. In Real-Time Systems Symposium, pages 339-349, 2010.
15. M. Negrean, S. Schliecker, and R. Ernst. Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources. In Design, Automation, Test in Europe Conference, pages 524-529, 2009.
16. R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley. A predictable execution model for cots-based embedded systems. In Real-Time and Embedded Technology and Applications Symposium, pages 269-279, 2011.
17. R. Pellizzoni, B. D. Bui, M. Caccamo, and L. Sha. Coscheduling of cpu and i/o transactions in cots-based embedded systems. In Real-Time Systems Symposium, pages 221-231, 2008.
18. R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele. Worst case delay analysis for memory interference in multicore systems. In Design, Automation, Test in Europe Conference, pages 741-746, 2010.
19. T. Pop, P. Pop, P. Eles, Z. Peng, and A. Andrei. Timing analysis of the FlexRay communication protocol. Real-Time Systems, 39(1):205-235, 2008.
20. S. Schliecker, M. Negrean, and R. Ernst. Bounding the shared resource load for the performance analysis of multiprocessor systems. In Design, Automation, Test in Europe Conference, pages 759-764, 2010.
21. A. Schranzhofer, J.-J. Chen, and L. Thiele. Timing analysis for TDMA arbitration in resource sharing systems. In Real-Time and Embedded Technology and Applications Symposium, pages 215-224, 2010.
22. A. Schranzhofer, R. Pellizzoni, J.-J. Chen, L. Thiele, and M. Caccamo. Worst-case response time analysis of resource access models in multi-core systems. In Design Automation Conference, pages 332-337, 2010.
23. A. Schranzhofer, R. Pellizzoni, J.-J. Chen, L. Thiele, and M. Caccamo. Timing analysis for resource access interference on adaptive resource arbiters. In Real-Time and Embedded Technology and Applications Symposium, pages 213-222, 2011.
24. L. Thiele, S. Chakraborty, and M. Naedele. Real-time calculus for scheduling hard real-time systems. In Symposium on Circuits and Systems, volume 4, pages 101-104, 2000.
25. R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(7):966-978, 2009.
26. S. Yovine. Model checking timed automata. In Lectures on Embedded Systems, pages 114-152. Springer, 1998.