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Volumn , Issue , 2010, Pages 332-337

Worst-case response time analysis of resource access models in multi-core systems

Author keywords

Scheduling; Shared resources; TDMA

Indexed keywords

ACCESS MODELS; COMPLETION TIME; CORE SYSTEMS; CRITICAL RESOURCES; HYBRID-ACCESS; MULTI-CORE SYSTEMS; MULTI-PROCESSORS; READ SENSOR; REAL-TIME TASKS; RESOURCE ACCESS; RESPONSE TIME; SCHEDULABILITY; SEQUENTIAL MODEL; SHARED MEMORIES; SHARED RESOURCES; TDMA; THREE MODELS; TIME TRIGGERED; TIME-CRITICAL SYSTEMS; WORST CASE RESPONSE TIME;

EID: 77956222606     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837359     Document Type: Conference Paper
Times cited : (33)

References (8)
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  • 2
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    • M. Negrean, S. Schliecker, and R. Ernst. Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources. In DATE '09., pages 524-529.
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  • 3
    • 67249152411 scopus 로고    scopus 로고
    • Coscheduling of CPU and I/O transactions in COTS-based embedded systems
    • Dec
    • R. Pellizzoni, B. D. Bui, M. Caccamo, and L. Sha. Coscheduling of CPU and I/O transactions in COTS-based embedded systems. In RTSS, Dec 2008.
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    • Pellizzoni, R.1    Bui, B.D.2    Caccamo, M.3    Sha, L.4
  • 5
    • 48649100636 scopus 로고    scopus 로고
    • Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip
    • J. Rosen, A. Andrei, P. Eles, and Z. Peng. Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip. In RTSS, pages 49-60, 2007.
    • (2007) RTSS , pp. 49-60
    • Rosen, J.1    Andrei, A.2    Eles, P.3    Peng, Z.4
  • 6
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    • Reliable performance analysis of a multicore multithreaded system-on-chip
    • S. Schliecker, M. Negrean, G. Nicolescu, P. Paulin, and R. Ernst. Reliable performance analysis of a multicore multithreaded system-on-chip. In CODES/ISSS, pages 161-166, 2008.
    • (2008) CODES/ISSS , pp. 161-166
    • Schliecker, S.1    Negrean, M.2    Nicolescu, G.3    Paulin, P.4    Ernst, R.5
  • 8
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    • Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
    • R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-critical Embedded Systems. IEEE TCAD, 28(7):966-978, 2009.
    • (2009) IEEE TCAD , vol.28 , Issue.7 , pp. 966-978
    • Wilhelm, R.1    Grund, D.2    Reineke, J.3    Schlickling, M.4    Pister, M.5    Ferdinand, C.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.