Integration of InGaAs channel n-MOS devices on 200mm Si wafers using the aspect-ratio-trapping technique

ECS Transactions

Volumn 45, Issue 4, 2012, Pages 115-128

  Waldron, Niamh ^a   Wang, Gang ^a,b   Nguyen, Ngoc Duy ^a,c   Orzali, Tommaso ^a   Merckling, Clement ^a   Brammertz, Guy ^a   Ong, Patrick ^a   Winderickx, Gillis ^a   Hellings, Geert ^a   Eneman, Geert ^a   Caymax, Matty ^a   Meuris, Marc ^a   Horiguchi, Naoto ^a   Thean, Aaron ^a  

^a IMEC   (Belgium)

^b MEMC   (United States)

^c UNIVERSITY OF LIÈGE   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; BUFFER LAYERS; CMOS INTEGRATED CIRCUITS; GALLIUM COMPOUNDS; GRAPHENE; III-V SEMICONDUCTORS; INDIUM PHOSPHIDE; MOS DEVICES; SEMICONDUCTING INDIUM; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTING INDIUM PHOSPHIDE; SEMICONDUCTOR ALLOYS; SEMICONDUCTOR QUANTUM WELLS; SILICON WAFERS; SUBSTRATES;

BACKGROUND DOPING; DRAIN LEAKAGE; INP SUBSTRATES; PLANAR SUBSTRATE; SELECTIVE EPITAXIAL GROWTH; SOURCE/DRAIN REGIONS; STANDARD CMOS; TRAPPING TECHNIQUES;

MOSFET DEVICES;

EID: 84869040528     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3700460     Document Type: Conference Paper

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