Instruction set architecture extensions for a dynamic task scheduling unit

Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Volumn , Issue , 2012, Pages 249-254

  Arnold, Oliver ^a   Noethen, Benedikt ^a   Fettweis, Gerhard ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

dynamic task scheduling; heterogeneous MPSoC; instruction set extension

Indexed keywords

DYNAMIC DATA; DYNAMIC TASK SCHEDULING; HETEROGENEOUS MPSOC; HETEROGENEOUS MULTIPROCESSOR SYSTEMS; INSTRUCTION SET ARCHITECTURE; INSTRUCTION SET EXTENSION; ON CHIPS; PERFORMANCE IMPROVEMENTS; PROCESSING ELEMENTS; TASK-SCHEDULING; TOOL FLOW;

COMPUTER ARCHITECTURE; DATA TRANSFER; MANAGERS; MULTIPROCESSING SYSTEMS; MULTITASKING; SCHEDULING ALGORITHMS;

INFORMATION MANAGEMENT;

EID: 84867817824     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2012.51     Document Type: Conference Paper

References (14)

1. Wang, A.; Killian, E.; Maydan, D.; Rowen, C.; , "Hardware/software instruction set configurability for system-on-chip processors," Design Automation Conference, 2001. Proceedings , vol., no., pp. 184-188, 2001.
2. Potlapally, N.R.; Ravi, S.; Raghunathan, A.; Lee, R.B.; Jha, N.K.; , "Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.15, no.5, pp.605-609, May 2007.
3. Chormoviti, A.; Vassiliadis, N.; Theodoridis, G.; Nikolaidis, S.; , "Enhancing Embedded Processors with Specific Instruction Set Extensions for Network Applications," Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2005. IDAACS 2005. IEEE , pp.199-203, 5-7 Sept. 2005.
4. K. Asanovic et al., "The landscape of parallel computing research: a view from Berkeley," Electrical Engineering and Computer Sciences, University of California, Berkeley, Long Beach, CA, USA, Tech. Rep., Dec. 2006.
5. Johns, C. R.; Brokenshire, D. A., "Introduction to the Cell Broadband Engine Architecture," IBM Journal of Research and Development , vol.51, no.5, pp.503-519, Sept. 2007.
6. T. Limberg, M. Winter, M. Bimberg, R. Klemm et al, "A Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for Software Defined Radio", DAC/ISSCC Student Design Contest, 2009.
7. O. Arnold, and G. Fettweis, "On the Impact of Dynamic Task Scheduling in Heterogeneous MPSoCs," Embedded Computer Systems (SAMOS), 2011 International Conference on, pp.17-24, 18-21 July 2011.
8. M. Winter, and G. Fettweis, "Guaranteed Service Virtual Channel Allocation in NoCs for Run-Time Task Scheduling," in Proceedings of the Design Automation and Test in Europe (DATE'11), Grenoble, France, March 2011.
9. http://www.tensilica.com, March 2012.
10. http://www.synopsys.com, March 2012.
11. O. Arnold, and G. Fettweis, " Power Aware Heterogeneous MPSoC with Dynamic Task Scheduling and Increased Data Locality for Multiple Applications," Embedded Computer Systems (SAMOS), 2010 International Conference on, pp.110-117, 19-22 July 2010.
12. J. Castrillon, D. Zhang, T. Kempf, B. Vanthournout, R. Leupers, and G. Ascheid "Task Management in MPSoCs: An ASIP Approach", International Conference on Computer-Aided Design, 2009.
13. Bellens, P.; Perez, J.M.; Badia, R.M.; Labarta, J., "CellSs: a Programming Model for the Cell BE Architecture," in SC'06, Proceedings of the Supercomputing conference, 2006.
14. J. Lee, V. J. Mooney III, A. Daleby, K. Ingström, T. Klevin, and L. Lindh, "A comparison of the RTU hardware RTOS with a hardware/software RTOS", In ASP-DAC '03, Proceedings of the Asia and South Pacific Design Automation Conference, 2003.