Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Volumn , Issue , 2011, Pages

  Nakamura, Tomoji ^a   Kitada, Hideki ^a,b   Mizushima, Yoriko ^a,b   Maeda, Nobuhide ^b   Fujimoto, Koji ^b   Ohba, Takayuki ^b  

^a FUJITSU LABORATORIES LTD   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATIVE STUDIES; ETCHING PROCESS; FEM SIMULATIONS; MICRO-STEPS; ROUGHNESS EFFECTS; SIDE WALLS; SIDEWALL ROUGHNESS; TEM ANALYSIS;

ETCHING; FINITE ELEMENT METHOD; STRESS CONCENTRATION;

LEAKAGE CURRENTS;

EID: 84866864616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2012.6262948     Document Type: Conference Paper

References (11)

1. A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, S. Pargfrieder, B.Swinnen, and E. Beyne, "Simultaneous Cu-Cu and Compliant Dielectric Bonding for 3D Stacking of ICs" IEEE Proc. of IITC, pp.207-209, 2007.
2. F. Liu, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi et al., "A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding" in IEDM Tech. Dig., pp. 599, 2008.
3. Nobuaki Miyakawa, "A 3D prototyping chip based on a wafer-level stacking technology", in Proc. of ASP-DAC, pp.416-420, 2009.
4. N. Maeda, H. Kitada1, K. Fujimoto, K. Suzuki, T. Nakamura and T. Ohba, "Novel and Production-Worthy Wafer-on-a-Wafer (WOW) Technology Using Self-Aligned TSV (SALT) Interconnects," Proc. of Adv. Metal. Conf. , pp.501-505, 2008.
5. T. Ohba, N. Maeda, H. Kitada, K. Fujimoto, K. Suzuki, T. Nakamura et al., "Thinned Wafer Multi-stack 3DI Technology," Microelectronic Eng., Elsevier, 87 pp. 485-490, 2010.
6. T. Ohba et al., Microelectronic Eng. 87, pp.485, 2010.
7. H. Kitada, N. Maeda, K. Fujimoto, K. Suzuki, T. Nakamura, T. Ohba et al, "Stress Sensitivity Analysis on TSV Structure of Wafer-on-a-Wafer (WOW) by the Finite Element Method (FEM)," IEEE Proc. of IITC, pp.107-109, 2009.
8. J. C. Lin, W.C. Chiou, K.F Yang, H.B. Chang, Y.C. Lin, E.B. Liao et al., "High Density 3D Integration using CMOS Foundry Technologies for 28 nm node and beyond", in IEDM Tech. Digest 2.1.1., 2010.
9. H. Kitada, N. Maeda, K. Fujimoto, Y. Mizushima, Y. Nakata, T. Nakamura, and T. Ohba, "Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology", Jpn. J. Appl. Phys. 50, 05ED02, 2011.
10. H. Kitada, Y. Morikawa, N. Maeda, K. Fujimoto, Y. Mizushima, T. Nakamura, and T. Ohba, "Surface micro roughness induced leakage current for Through-Silicon Via interconnects" Proc. of Adv. Metal. Conf. 13-1. 2011.
11. Y. Morikawa, T. Murayama, K. Suu, "High Etch Rate of TSV using by Ultra Self-Confined VHF-CCP", Proc. of AVS 57th, pp.121, 2010.