A novel SEU, MBU and SHE handling strategy for xilinx Virtex-4 FPGAS

FPL 09: 19th International Conference on Field Programmable Logic and Applications

Volumn , Issue , 2009, Pages 569-573

  Iturbe, X ^a   Azkarate, M ^a   Martnez I ^a   Perez, J ^a   Astarloa, A ^b  

^a IK4 IKERLAN   (Spain)

^b UNIVERSITY OF THE BASQUE COUNTRY UPV EHU   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BIT STREAM; BITSTREAM DOMAIN; HARDWARE ERROR; MITIGATION STRATEGY; MULTIPLE BIT UPSET; RE-CONFIGURABLE; SINGLE EVENT UPSETS; SYSTEM AVAILABILITY;

ELECTRIC NETWORK ANALYSIS; URANIUM POWDER METALLURGY;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70450092853     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2009.5272410     Document Type: Conference Paper

References (12)

1. Xilinx Inc., "Reliability report, 4th quarter 2008," UG116.
2. M. Berg, "Assessing and mitigating radiation effects in Xilinx FPGAs," JPL Publication, 2008.
3. C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol. 23, no. 4, pp. 14-19, 2003.
4. S. Suresh, M. Prasanth, X. Yuan, N. Vijaykrishnan, and S. Karthik, "FLAW: FPGA lifetime awareness," in IEEE Design Automation Conference, 2006, pp. 630-635.
5. Xilinx Inc., "Xilinx TMRTool user guide," UG156, 2006.
6. K. Chapman and L. Jones, "SEU strategies for Virtex-5 devices," Xilinx Inc. XAPP864, 2009.
7. A. Lesea and P. Alfke, "Xilinx FPGAs overcome the side effects of sub-90 nm technology," Xilinx Inc. WP256, 2007.
8. M. Berg, C. Poivey, D. Petrick, D. Espinosa, A. Lesea, K. A. Label, M. Friendlich, H. Kim, and A. Phan, "Effectiveness of internal versus external SEU scrubbing mitigation strategies in a Xilinx FPGA: Design, test, and analysis," IEEE Trans. on Nuclear Science, vol. 55, no. 4, pp. 2259-2266, 2008.
9. S. Pontarelli, M. Ottavi, V. Vankamamidi, G. Cardarilli, F. Lombardi, and A. Salsano, "Analysis and evaluations of reliability of reconfigurable FPGAs," in Journal of Electronic Testing, vol. 24, no. 1, 2008, pp. 105-116.
10. W. E. Cory, D. P. Schultz, and S. P. Young, "Error checking parity and syndrome of a block of data with relocated parity bits," U.S. Patent 7 426 678, Sept. 16, 2008.
11. A. Avizienis, J. C. Laprie, B. Randell, and C. Landwehr, "Basic concepts and taxonomy of dependable and secure computing," IEEE Trans. on Dependable Secure Comput., vol. 1, no. 1, pp. 11-33, 2004.
12. G. Asadi and M. B. Tahoori, "Soft error rate estimation and mitigation for SRAM-based FPGAs," ACM International Symposium on Field-Programmable Gate Arrays, pp. 149-160, 2005.