FPGA implementation of the generalized delayed signal cancelation - Phase locked loop method for detecting harmonic sequence components in three-phase signals

IEEE Transactions on Industrial Electronics

Volumn 60, Issue 2, 2013, Pages 645-658

  Nascimento, Paulo S B ^a   De Souza, Helber E P ^a   Neves, Francisco A S ^b   Limongi, Leonardo R ^b  

^a INSTITUTO FEDERAL DE EDUCAÇÃO   (Brazil)

^b FEDERAL UNIVERSITY OF PERNAMBUCO   (Brazil)

Author keywords

Digital signal processor (DSP); field programmable gate array (FPGA); generalized delayed signal cancelationphase locked loop (GDSC PLL); phase detection; three phase system

Indexed keywords

ACTIVE FILTERS; ALGORITHMS; DIGITAL SIGNAL PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RENEWABLE ENERGY RESOURCES;

ACTIVE POWER FILTER; COMPUTATIONAL EFFORT; DETECTION TECHNIQUE; DSP IMPLEMENTATION; DYNAMIC VOLTAGE RESTORER (DVR); EFFICIENT DETECTION; EXECUTION TIME; FPGA IMPLEMENTATIONS; GENERALIZED DELAYED SIGNAL CANCELATIONPHASE LOCKED LOOP (GDSC-PLL); PHASE DETECTION; POWER SYSTEMS PROTECTION; PROPOSED ARCHITECTURES; RENEWABLE ENERGY SYSTEMS; SAMPLING PERIOD; SEQUENCE COMPONENTS; THREE PHASE SYSTEM;

SIGNAL DETECTION;

EID: 84866614499     PISSN: 02780046     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIE.2012.2206350     Document Type: Article

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