A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 76-77

  Tan, Y ^a   Duster, J ^a   Fu, C T ^a   Alpman, E ^a   Balankutty, A ^a   Lee, C ^a   Ravi, A ^a   Pellerano, S ^a   Chandrashekar, K ^a   Kim, H ^a   Carlton, B ^a   Suzuki, S ^a   Shafi, M ^a   Palaskas, Y ^a   Lakdawala, H ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

802.11G; T/R SWITCH; WLAN TRANSCEIVERS;

VLSI CIRCUITS;

TRANSCEIVERS;

EID: 84866599019     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243797     Document Type: Conference Paper

References (7)

1. Y. Tan, et al., "A flip-chip packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS", ISSCC 2011, pp. 426-428.
2. C.T. Fu, et al, "A 2.5GHz, 32nm, 0.35mm2, 3.5dB NF, -5dBm P1dB, fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection", ISSCC 2011, pp. 56-57.
3. A. Ravi, et al, "A 9.2-12GHz, 90nm digital fractional-N synthesizer with stochastic TDC calibration and -35/-41dBc integrated phase noise in the 5/2.5GHz bands", VLSI 2010, p143.
4. K. Chandrashekar, et al, "A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multi-standard SoC radios with on-the-fly interference management", to appear at ISSCC 2012.
5. P. VanDerVoorn, et al, "A 32nm low power RF CMOS SOC technology featuring high-k/metal gate" VLSI 2010, pp.137-138.
6. C. Chang, et al., "A CMOS transceiver with internal PA and digital pre-distortion for WLAN 802.11a/b/g/n applications" RFIC 2010, pp435-438.
7. S. Abdollahi-Alibeik et al., "A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC", ISSCC 2011, pp170-171.