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Volumn , Issue , 2010, Pages 143-144

A 9.2-12GHz, 90nm digital fractional-N synthesizer with stochastic TDC calibration and -35/-41dBc integrated phase noise in the 5/2.5GHz bands

Author keywords

802.11n; 802.16e; Digital PLL; Frequency synthesizer; TDC calibration and phase noise minimization

Indexed keywords

802.11N; 802.16E; 90NM CMOS; DIGITAL PLL; FRACTIONAL-N SYNTHESIZER; GHZ BAND; MINIMIZATION ALGORITHMS; TDC CALIBRATION AND PHASE NOISE MINIMIZATION; TIME TO DIGITAL CONVERSION;

EID: 77958009478     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560321     Document Type: Conference Paper
Times cited : (18)

References (6)
  • 2
    • 68549111107 scopus 로고    scopus 로고
    • A digital intensive fractional-N PLL and all-digital self-calibration schemes
    • Aug.
    • P.-Y.Wang, J.-H. Zhan, H.-H. Chang, and H-M. S. Chang, "A digital intensive fractional-N PLL and all-digital self-calibration schemes," IEEE J. Solid-State Circuits, pp. 2182-2192, Aug. 2009.
    • (2009) IEEE J. Solid-State Circuits , pp. 2182-2192
    • Wang, P.-Y.1    Zhan, J.-H.2    Chang, H.-H.3    Chang, H.-M.S.4
  • 3
    • 49549112279 scopus 로고    scopus 로고
    • A 3 GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction
    • San Francisco, CA, Feb.
    • C. Weltin-Wu, E. Temporiti, D. Baldi, and F. Svelto, "A 3 GHz fractional-N all-digital PLL with precise time-to-digital converter calibration and mismatch correction," in IEEE ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2008, pp. 344-345.
    • (2008) IEEE ISSCC Dig. Tech. Papers , pp. 344-345
    • Weltin-Wu, C.1    Temporiti, E.2    Baldi, D.3    Svelto, F.4
  • 4
    • 70350592003 scopus 로고    scopus 로고
    • A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution
    • Oct.
    • M. Lee, M. E. Heidari, and A. A. Abidi, "A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution," ," IEEE J. Solid-State Circuits, pp. 2808-2816, Oct. 2009.
    • (2009) IEEE J. Solid-State Circuits , pp. 2808-2816
    • Lee, M.1    Heidari, M.E.2    Abidi, A.A.3
  • 5
    • 0035696224 scopus 로고    scopus 로고
    • A filtering technique to lower LC oscillator phase noise
    • DOI 10.1109/4.972142, PII S0018920001093167, 2001 ISSCC: Analog, Wireline, Wireless, and Imagers, Mems, and Displays
    • E. Hegazi, H. Sjoland, A. A. Abidi, "A filtering technique to lower LC oscillator phase noise," IEEE J. of Solid-State Circuits, pp. 1921 - 1930, Dec. 2001. (Pubitemid 34069258)
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.12 , pp. 1921-1930
    • Hegazi, E.1    Sjoland, H.2    Abidi, A.A.3
  • 6
    • 33947615213 scopus 로고    scopus 로고
    • Statistical linearity calibration of time-to-digital converters using a free-running ring oscillator
    • J. Rivoir, "Statistical linearity calibration of time-to-digital converters using a free-running ring oscillator," in Proc. 2006 IEEE Asian Test Symp., pp. 45-50.
    • Proc. 2006 IEEE Asian Test Symp. , pp. 45-50
    • Rivoir, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.