A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 426-427

  Tan, Yulin ^a   Xu, Hongtao ^a   El Tanani, Mohammed A ^a   Taylor, Stewart ^a   Lakdawala, Hasnain ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EFFICIENCY; ELECTRONICS PACKAGING; POWER AMPLIFIERS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; THERMOANALYSIS;

AVERAGE OUTPUT POWER; CLASS-AB POWER AMPLIFIERS; CONDUCTIVE SUBSTRATES; DIGITAL PREDISTORTION; HIGH POWER AMPLIFIER; HIGH SUPPLY VOLTAGES; POWER-HANDLING CAPABILITY; THERMAL DISSIPATION;

FLIP CHIP DEVICES;

EID: 79955715537     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746381     Document Type: Conference Paper

References (5)

1. D. Chowdhury, et al., "A Single-Chip Highly Linear 2.4GHz 30dBm Power Ampifier in 90nm CMOS", IEEE ISSCC Dig. Tech., 2009, pp. 378-379, Feb. 2009.
2. A. Afsahi, et al., " Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2x2 802.11n MIMO WLAN SoC", IEEE JSSC vol.45, no.5, pp. 955-965, May 2010.
3. M. Terrovitis, et al., "A 1x1 802.11n WLAN SoC with fully integrated RF front-end utilizing PA linearization", in Proc. of ESSCIRC, pp. 224-227, Sept. 2009.
4. H. Xu, et al.,"A Highly Linear 25dBm Outphasing Power Amplifier in 32nm CMOS for WLAN application", Proc. of ESSCIRC, pp.306-309, Sept. 2010.
5. C.-H. Jan, et al., "A 32nm SoC platform technology with 2nd generation high k/metal gate transistors optimized for ultra low power, high performance, and high density product applications ", IEEE IEDM Tech. Dig., pp. 1-4, Dec. 2009.