A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 137-138

  Van Der Voorn, P ^a   Agostinelli, M ^a   Choi, S J ^a   Curello, G ^a   Deshpande, H ^a   El Tanani, M A ^a   Hafez, W ^a   Jalan, U ^a   Janbay, L ^a   Kang, M ^a   Koh, K J ^a   Komeyli, K ^a   Lakdawala, H ^a   Lin, J ^a   Lindert, N ^a   Mudanai, S ^a   Park, J ^a   Phoa, K ^a   Rahman, A ^a   Rizk, J ^a   Rockford, L ^a   Sacks, G ^a   Soumyanath, K ^a   Tashiro, H ^a   Taylor, S ^a   Tsai, C ^a   Xu, H ^a   Xu, J ^a   Yang, L ^a   Young, I ^a   Yeh, J Y ^a   Yip, J ^a   Bai, P ^a   Jan, C H ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BREAKDOWN VOLTAGE; HIGH-Q INDUCTORS; LOW LEAKAGE; LOW POWER RF; METAL-GATE; NOISE ISOLATION; POWER AMPLIFIER TRANSISTORS; TRANSISTOR ARCHITECTURE;

MOS DEVICES; POWER AMPLIFIERS;

TECHNOLOGY;

EID: 77957859644     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556201     Document Type: Conference Paper

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4. C. Auth et al, VLSI Symp. Proc., p. 128-129 (2008).
5. C.-H. Jan et al, IEDM Tech. Digest, p. 637-640 (2008).
6. P. Packan et al, IEDM Tech. Digest, p.28-4 (2009).