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Volumn 1, Issue , 2006, Pages 652-669

Why did my chip do that? A survey of on-chip debug and diagnosis techniques

Author keywords

[No Author keywords available]

Indexed keywords

DIAGNOSIS TECHNIQUES; ON CHIP MEASUREMENTS; ON CHIPS;

EID: 84866434187     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (13)
  • 3
    • 0036575031 scopus 로고    scopus 로고
    • Design for debug:Catching design errors in digital chips
    • May-June
    • Vermeulen and Goel. "Design for Debug: Catching Design Errors in Digital Chips". IEEE Design and Test of Computers, May-June 2002, pages 37-45.
    • (2002) IEEE Design and Test of Computers , pp. 37-45
    • Vermeulen1    Goel2
  • 4
    • 84882890334 scopus 로고    scopus 로고
    • DesignWare PHY and SERDES Technologies. website
    • DesignWare PHY and SERDES Technologies. Synopsys website http://www.synopsys.com/products/designware/serdestech.html.
    • Synopsys
  • 9
    • 84866353848 scopus 로고    scopus 로고
    • IEEE Standard Test Access Port and Boundary-Scan Architecture Institute of Electrical and Electronics Engineers 14-Jun-, ISBN: 0738129445
    • IEEE Standard Test Access Port and Boundary-Scan Architecture Institute of Electrical and Electronics Engineers 14-Jun-2001 ISBN: 0738129445.
    • (2001)
  • 10
    • 84866429660 scopus 로고    scopus 로고
    • Introduction to on-chip debug
    • March
    • Berger and Barr. "Introduction to On-Chip Debug" Embedded Systems Programming, March 2003, pp. 47-48.
    • (2003) Embedded Systems Programming , pp. 47-48
    • Berger1    Barr2
  • 11
    • 84866410447 scopus 로고    scopus 로고
    • http://www.nexus5001.org/.
  • 12
    • 84866353849 scopus 로고    scopus 로고
    • IEEE PSL Standards
    • IEEE PSL Standards: http://www.eda.org/ieee-1850/.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.