Design space exploration of workload-specific last-level caches

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 243-248

  Swaminathan, Karthik ^a   Kultursay, Emre ^a   Saripalli, Vinay ^a   Narayanan, Vijaykrishnan ^a   Kandemir, Mahmut ^a  

^a The Pennsylvania State University   (United States)

Author keywords

cache leakage; hp; lstp transistors; power gated drowsy caches; stt ram; tunnel fets

Indexed keywords

AVAILABLE ENERGY; CACHE ENERGY; DESIGN SPACE EXPLORATION; DROWSY CACHE; ENERGY EFFICIENT; HP; LEAKAGE POWER; POWER GATED/DROWSY CACHES; STT-RAM; SYSTEM DESIGNERS; TECHNOLOGY-BASED; TUNNEL-FETS;

ENERGY EFFICIENCY; LOW POWER ELECTRONICS;

LEAKAGE CURRENTS;

EID: 84865536839     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333718     Document Type: Conference Paper

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