Automatic bus macro placement for partially FPGA designs

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 269-272

  Carver, Jeffrey M ^a   Pittman, Richard N ^b   Forin, Alessandro ^b  

^a UTAH STATE UNIVERSITY   (United States)

^b MICROSOFT RESEARCH   (United States)

Author keywords

Dynamic partial reconfiguration; eMIPS; Floor planning; Reconfigurable computing

Indexed keywords

COMBINED DESIGN; CONFIGURABLE LOGIC; CONNECTION POINTS; DESIGN PRACTICE; DESIGN SPACE EXPLORATION; DYNAMIC PARTIAL RECONFIGURATION; EMIPS; FLOOR-PLANNING; FPGA DESIGN; OPTIMAL PLACEMENTS; RE-CONFIGURABLE; RECONFIGURABLE COMPUTING; RUNTIME; TIMING CONSTRAINTS;

BUSES; COMPUTER SCIENCE; DESIGN; FLOORS; HEALTH; LOGIC GATES; SPACE RESEARCH; TIMING CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 67650671573     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508175     Document Type: Conference Paper

References (8)

1. http://xilinx.com/support/prealounge/protected/index.htm
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