COMMA: A communications methodology for dynamic module reconfiguration in FPGAs

Proceedings - 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2006

Volumn , Issue , 2006, Pages 273-274

  Koh, Shannon ^a   Diessel, Oliver ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 34547401647     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2006.32     Document Type: Conference Paper

References (7)

1. C. Bobda, A. Ahmadinia, M. Majer, J. Teich, S. Fekete, and J.v.d. Veen. DYNOC: A dynamic infrastructure for communication in dynamically reconfigurable devices. In FPL 2005, pp. 153-158.
2. G. Brebner. The swappable logic unit: a paradigm for virtual hardware. In FCCM97, pp. 77-86.
3. L. Chaouat, S. Garin, A. Vachoux, and D. Mlynek. Rapid prototyping of hardware systems via model reuse. In 8th IEEE Intl Workshop on Rapid System Prototyping, 1997, pp. 150-156.
4. H. Kalte, M. Porrmann, and U. Ruckert. System-on-programmable-chip approach enabling online fine-grained Dplacement. In IPDPS 2004, p. 141.
5. T. Marescaux, A. Bartic, D. Verkest, S. Vernalde, and R. Lauwereins. Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs. In FPL 2002, 795-805.
6. P. Sedcole, B. Blodget, J. Anderson, P. Lysaght, and T. Becker. Modular partial reconfiguration in Virtex FPGAs. In FPL 2005, pp. 211-216.
7. Xilinx Inc. Two flows for partial reconfiguration: module based or difference based. Xilinx App. Note 290 Sep., 2004.