Modeling of a pair of annular through silicon vias (TSV)

2011 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2011

Volumn , Issue , 2011, Pages

  Xu, Xiao Long ^a   Zhao, Wen Sheng ^b   Yin, Wen Yan ^a,b  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

^b ZHEJIANG UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE EFFECT; CHARACTERISTIC IMPEDANCE; EFFECTIVE CAPACITANCE; LUMPED-ELEMENT CIRCUIT MODEL; TEMPERATURE DEPENDENT; THROUGH SILICON VIAS;

PACKAGING;

CAPACITANCE;

EID: 84864259009     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDAPS.2011.6213740     Document Type: Conference Paper

References (7)

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3. V. F. Pavlidis and E. G. Friedman, "Interconnect-based design methodologies for three-dimensional integrated circuits," Proc. IEEE, vol. 97, no. 1, pp. 123-140, Jan. 2009.
4. B. Xie, X. Q. Shi, C. H. Chung, and S. W. R. Lee, "Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design," Electronic Components and Technology Conference, pp. 1166-1172, 2010.
5. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, and R. Tummala, "Electrical modeling of annular and co-axial TSVs considering MOS capacitance effects," IEEE Conf. EPEPS, pp. 117-120, Oct. 2009.
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