A study of on-chip stacked multiloop spiral inductors

IEEE Transactions on Electron Devices

Volumn 55, Issue 11, 2008, Pages 3236-3245

  Yang, Kai ^a,b   Yin, Wen Yan ^a   Shi, Jinglin ^c   Kang, Kai ^c   Mao, Jun Fa ^a   Zhang, Y P ^d  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

^b CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^c INSTITUTE OF MICROELECTRONICS   (Singapore)

^d NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Differential topology; Inductance; Partial element equivalent circuit (PEEC) method; Patterned ground shields (PGSs); Q factor; Resistance; Stacked multiloop spiral inductors

Indexed keywords

ELECTRIC INDUCTORS; INDUCTANCE; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); Q FACTOR MEASUREMENT; SILICON;

DIFFERENTIAL TOPOLOGY; PARTIAL-ELEMENT EQUIVALENT-CIRCUIT (PEEC) METHOD; PATTERNED GROUND SHIELDS (PGSS); Q-FACTOR; RESISTANCE; STACKED MULTILOOP SPIRAL INDUCTORS;

TOPOLOGY;

EID: 56549106455     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2004648     Document Type: Article

References (14)

1. Y. Cao, R. A. Groves, N. D. Zamdmer, J. O. Plouchart, R. A. Wachnik, X. J. Huang, T. J. King, and C. M. Hu, "Frequency-independent equivalent-circuit model for on-chip spiral inductors," IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 743-752, Mar. 2003.
2. F. Rotella, B. K. Bhattacharya, V. Blaschke, M. Matloubian, A. Brotman, Y. H. Cheng, R. Divecha, D. Howard, K. Lampaert, P. Miliozzi, M. Racanelli, P. Singh, and P. J. Zampardi, "A broad-band lumped element analytic model incorporating skin effect and substrate loss for inductors and inductor like components for silicon technology performance assessment and RFIC design," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1429-1441, Jul. 2005.
3. A. M. Niknejad and R. G. Meyer, "Analysis of eddy current losses over conductive substrates with applications to monolithic inductors and transformers," IEEE Trans. Microw. Theory Tech., vol. 49, no. 1, pp. 166-176, Jan. 2001.
4. J. Chen and J. J. Liu, "Modeling of on-chip differential inductors and transformers/baluns," IEEE Trans. Electron Devices, vol. 54, no. 2, pp. 369-371, Feb. 2007.
5. C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RFICs," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743-752, May 1998.
6. C. A. Chang, S. P. Tseng, J. Y. Chung, S. S. Jiang, and J. A. Yeh, "Characterization of spiral inductors with patterned floating structures," IEEE Trans. Microw. Theory Tech., vol. 52, no. 5, pp. 1375-1381, May 2004.
7. T. S. D. Cheung and J. R. Long, "Shielded passive device for silicon-based monolithic microwave and millimeter-wave integrated circuits," IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1183-1200, May 2006.
8. A. Zolfaghari, A. Chan, and B. Razavi, "Stacked inductors and transformers in CMOS technology," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
9. C.-C. Tang, C.-H. Wu, and S.-I. Liu, "Miniature 3-D inductors in standard CMOS process," IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-479, Apr. 2002.
10. W. Y. Yin, S. J. Pan, L. W. Li, and Y B. Gan, "Modeling on-chip circular double-spiral stacked inductors for RFICs," Proc. Inst. Elect. Eng.- Microw., Antennas Propag., vol. 150, no. 6, pp. 463-469, Dec. 2003.
11. J. Kuo, K.-Y Su, T.-Y. Liu, H.-H. Chen, and S.-J. Chung, "Analytical calculation for DC inductances of rectangular spiral inductors with finite metal thickness in the PEEC formulation," IEEE Microw. Wireless Compon. Lett., vol. 16, no. 2, pp. 69-71, Feb. 2006.
12. A. E. Ruehli, "Equivalent circuit models for three-dimensional multiconductor systems," IEEE Trans. Microw. Theory Tech., vol. MTT-22, no. 3, pp. 216-221, Mar. 1974.
13. D. R. Wilton, S. Rao, A. Glisson, D. Schaubert, O. Al-bundrak, and C. Butler, "Potential integrals for uniform and linear source distributions on polygonal and polyhedral domains," IEEE Trans. Antennas Propag., vol. AP-32, no. 3, pp. 276-281, Mar. 1984.
14. K. L. Wu, L. K. Yeung, and Y. Ding, "An efficient PEEC algorithm for modeling of LTCC RE circuits with finite metal strip thickness," IEEE Microw. Wireless Compon. Lett., vol. 13, no. 9, pp. 390-392, Sep. 2003.