A framework for reliability assessment in multilevel phase-change memory

2012 4th IEEE International Memory Workshop, IMW 2012

Volumn , Issue , 2012, Pages

  Pozidis, H ^a   Papandreou, N ^a   Sebastian, A ^a   Mittelholzer, T ^a   BrightSky, M ^b   Lam, C ^b   Eleftheriou, E ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE RELIABILITY; EMPIRICAL MODEL; EXPERIMENTAL DATA; MEMORY TECHNOLOGY; PHASE CHANGES; RELIABILITY ASSESSMENTS;

RELIABILITY ANALYSIS;

PHASE CHANGE MEMORY;

EID: 84864127801     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2012.6213671     Document Type: Conference Paper

References (11)

1. R. F. Freitas and W.W.Wilcke, "Storage-class memory: The next storage system technology," IBM J. Res. Dev., vol. 52, pp. 439-447, 2008.
2. D. Fugazza, D. Ielmini, S. Lavizzari, and A. L. Lacaita, "Experimental investigation of transport properties in chalcogenide materials through 1/f noise measurements," Appl. Phys. Lett., vol. 88.
3. P. Fantini, G. Betti Beneventi, A. Calderoni, L. Larcher, P. Pavan, and F. Pellizzer, "Characterization and modelling of low-frequency noise in PCM devices," in IEDM Tech. Dig., 2008, pp. 219-222.
4. D. Fugazza, D. Ielmini, S. Lavizzari, and A. L. Lacaita, "Distributed- Poole-Frenkel modeling of anomalous resistance scaling and fluctuations in phase-change memory (PCM) devices," in IEDM Tech. Dig., 2009, pp. 723-726.
5. -, "Random telegraph signal noise in phase change memory devices," in Proc. IRPS, 2010, pp. 743-749.
6. D. Ielmini, D. Sharma, S. Lavizzari, and A. L. Lacaita, "Reliability impact of chalcogenide-structure relaxation in phase-change memory (PCM) cellsPart I: experimental study," IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1070-1077, 2009.
7. M. Boniardi, D. Ielmini, S. Lavizzari, A. L. Lacaita, A. Redaelli and A. Pirovano, "Statistics of resistance drift due to structural relaxation in phase-change memory arrays," IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2690-2696, 2010.
8. A. Calderoni, M. Ferro, D. Ventrice, D. Ielmini, and P. Fantini, "RESET current distributions in phase change memories," in Proc. IRPS, 2010, pp. 738-742.
9. G. F. Close, U. Frey, M. Breitwisch, H. L. Lung, C. Lam, C. Hagleitner, and E. Eleftheriou, "Device, circuit and system-level analysis of noise in multi-bit phase-change memory," in IEDM Tech. Dig., 2010, pp. 660-663.
10. M. Breitwisch et al., "Novel lithography-independent pore phase change memory," in Proc. Symp. VLSI Tech., 2007, pp. 100-101.
11. N. Papandreou, H. Pozidis, A. Pantazi, A. Sebastian, M. Breitwisch, C. Lam, and E. Eleftheriou, "Programming algorithms for multilevel phase-change memory," in Proc. ISCAS, 2011, pp. 329-332.