Compiling for energy efficiency on timing speculative processors

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 1301-1308

  Sartori, John ^a   Kumar, Rakesh ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

binary optimization; computer architecture; energy efficiency; error resilience; timing speculation

Indexed keywords

BINARY OPTIMIZATION; COMPILER OPTIMIZATIONS; EFFICIENCY BENEFITS; ENERGY BENEFITS; ERROR RATE; ERROR RESILIENCE; HARDWARE SUPPORTS; IN-FIELD; PROGRAM BINARY; TIMING SPECULATION;

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; ERRORS; OPTIMIZATION; PROGRAM COMPILERS;

ENERGY EFFICIENCY;

EID: 84863541933     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228602     Document Type: Conference Paper

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