메뉴 건너뛰기




Volumn , Issue , 2012, Pages 741-746

Exploiting die-to-die thermal coupling in 3D IC placement

Author keywords

3D IC; temperature; TSV

Indexed keywords

FORCE-DIRECTED; HIGH-POWER; LOCAL POWER DENSITIES; LOGIC CELLS; THERMAL COUPLING; TSV; VERTICALLY ALIGNED;

EID: 84863541923     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228495     Document Type: Conference Paper
Times cited : (14)

References (7)
  • 1
    • 80052671580 scopus 로고    scopus 로고
    • Thermal-aware cell and through-silicon-via co-placement for 3D ICs
    • San Diego, CA, Jun. 5-9
    • J. Cong, G. Luo, and Y. Shi. Thermal-aware cell and through-silicon-via co-placement for 3D ICs. In Proc. ACM Design Automation Conf., pages 670-675, San Diego, CA, Jun. 5-9 2011.
    • (2011) Proc. ACM Design Automation Conf. , pp. 670-675
    • Cong, J.1    Luo, G.2    Shi, Y.3
  • 2
    • 0347409236 scopus 로고    scopus 로고
    • Efficient thermal placement of standard cells in 3D ICs using a force directed approach
    • San Jose, CA, Nov. 9-13
    • B. Goplen and S. Sapatnekar. Efficient thermal placement of standard cells in 3D ICs using a force directed approach. In Proc. IEEE Int. Conf. on Computer-Aided Design, pages 86-89, San Jose, CA, Nov. 9-13 2003.
    • (2003) Proc. IEEE Int. Conf. on Computer-Aided Design , pp. 86-89
    • Goplen, B.1    Sapatnekar, S.2
  • 3
    • 34547301387 scopus 로고    scopus 로고
    • Placement of 3D ICs with thermal and interlayer via considerations
    • San Diego, CA, June 4-8
    • B. Goplen and S. Sapatnekar. Placement of 3D ICs with thermal and interlayer via considerations. In Proc. ACM Design Automation Conf., pages 626-631, San Diego, CA, June 4-8 2007.
    • (2007) Proc. ACM Design Automation Conf. , pp. 626-631
    • Goplen, B.1    Sapatnekar, S.2
  • 4
    • 76349113557 scopus 로고    scopus 로고
    • A study of through-silicon-via impact on the 3D stacked IC layout
    • San Jose, CA, Nov. 2-5
    • D. H. Kim, K. Athikulwongse, and S. K. Lim. A study of through-silicon-via impact on the 3D stacked IC layout. In Proc. IEEE Int. Conf. on Computer-Aided Design, pages 674-680, San Jose, CA, Nov. 2-5 2009.
    • (2009) Proc. IEEE Int. Conf. on Computer-Aided Design , pp. 674-680
    • Kim, D.H.1    Athikulwongse, K.2    Lim, S.K.3
  • 6
    • 78650873482 scopus 로고    scopus 로고
    • Through-silicon-via management during 3D physical design: When to add and how many?
    • San Jose, CA, Nov. 7-11
    • M. Pathak, Y.-J. Lee, T. Moon, and S. K. Lim. Through-silicon-via management during 3D physical design: When to add and how many? In Proc. IEEE Int. Conf. on Computer-Aided Design, pages 387-394, San Jose, CA, Nov. 7-11 2010.
    • (2010) Proc. IEEE Int. Conf. on Computer-Aided Design , pp. 387-394
    • Pathak, M.1    Lee, Y.-J.2    Moon, T.3    Lim, S.K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.