Reconfigurable and parallelized network coding decoder for VANETs

Mobile Information Systems

Volumn 8, Issue 1, 2012, Pages 45-59

  Kim, Sunwoo ^a   Ro, Won W ^b  

^a Hyundai Motor Co   (South Korea)

^b Yonsei University   (South Korea)

Author keywords

FPGA; hardware accelerator; Network coding; VANETs

Indexed keywords

DECODING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NETWORK CODING; RECONFIGURABLE HARDWARE;

COEFFICIENT MATRIX; COEFFICIENT VECTOR; DATA-COMMUNICATION; DECODING PROCESS; DIFFERENT SIZES; EMBEDDED PROCESSORS; HARDWARE ACCELERATOR; OPERATING FREQUENCY; RE-CONFIGURABLE; RECEIVING NODES; VANETS; WIRED AND WIRELESS;

VEHICULAR AD HOC NETWORKS;

EID: 84863162296     PISSN: 1574017X     EISSN: 1875905X     Source Type: Journal    
DOI: 10.3233/MIS-2012-0130     Document Type: Article

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