A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

Microprocessors and Microsystems

Volumn 34, Issue 6, 2010, Pages 228-236

  Zhang, Yu ^a   Chen, Dongdong ^a   Choi, Younhee ^a   Chen, Li ^a   Ko, Seok Bum ^a  

^a UNIVERSITY OF SASKATCHEWAN   (Canada)

Author keywords

Elliptic curve cryptosystem; Instruction level parallelism; Polynomial basis

Indexed keywords

CLOCK CYCLES; CMOS TECHNOLOGY; CRITICAL PATHS; DATA DEPENDENCIES; ELLIPTIC CURVE; ELLIPTIC CURVE CRYPTOSYSTEM; ELLIPTIC CURVE POINT MULTIPLICATIONS; FINITE FIELDS; FPGA DEVICES; HARDWARE IMPLEMENTATIONS; INSTRUCTION LEVEL PARALLELISM; POLYNOMIAL BASIS; RISC CORE;

CMOS INTEGRATED CIRCUITS; CRITICAL PATH ANALYSIS; CRYPTOGRAPHY; HARDWARE;

GEOMETRY;

EID: 77954196120     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2010.04.006     Document Type: Article

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