FPGA implementations of LDPC over GF(2m) decoders

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2007, Pages 273-278

  Spagnol, Christian ^a   Marnane, William ^a   Popovici, Emanuel ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

Block codes; Decoding; FPGA; Galois fields

Indexed keywords

DECODING ALGORITHMS; FPGA; FPGA IMPLEMENTATIONS; GALOIS FIELDS; HARDWARE IMPLEMENTATIONS; LDPC CODES; LOW-DENSITY PARITY-CHECK CODES; SUPERIOR PERFORMANCES;

BLOCK CODES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; SIGNAL PROCESSING; TECHNICAL PRESENTATIONS;

DECODING;

EID: 47949130356     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2007.4387557     Document Type: Conference Paper

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