Improving FPGA routability using network coding

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2008, Pages 147-150

  Gulati, Kanupriya ^a   Khatri, Sunil R ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

FPGA; Network coding

Indexed keywords

COMMUNICATION NETWORKS; COST MODELS; CURRENT TECHNOLOGIES; FPGA; MCNC BENCHMARKS; NETWORK CODING; NETWORK THROUGHPUTS; NEW TECHNIQUES; RESOURCE UTILIZATIONS; ROUTABILITY; ROUTABILITY IMPROVEMENTS; TOOL SUITES; TRACK COUNTS; WIRE LENGTHS; WORST CASES;

COMPUTER NETWORKS; DELAY CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LAKES; METROPOLITAN AREA NETWORKS; PROGRAMMING THEORY; ROUTERS;

ROUTING ALGORITHMS;

EID: 56749142736     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1366110.1366147     Document Type: Conference Paper

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