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Volumn , Issue , 2011, Pages 230-233

An 80-dB SNR 4th-order discrete-time sigma-delta modulator

Author keywords

Analog to digital converter; Comparator metastability; Compensation capacitor; Discrete time modulator

Indexed keywords

ANALOG TO DIGITAL CONVERTERS; AUDIO APPLICATIONS; CLOCK GENERATOR; CMOS PROCESSS; COMPARATOR-METASTABILITY; COMPENSATION CAPACITOR; COMPENSATION CAPACITORS; DISCRETE-TIME; METASTABILITIES; QUANTIZERS; SAMPLING CLOCKS; SIGMA DELTA MODULATOR; SIGNAL BANDWIDTH; SIGNAL TO NOISE; SIGNAL TO NOISE AND DISTORTION RATIO; SINGLE-BIT; SUPPLY VOLTAGES; TOTAL POWER CONSUMPTION;

EID: 84863057618     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISICir.2011.6131938     Document Type: Conference Paper
Times cited : (1)

References (11)
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  • 4
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    • (2008) Proc. IEEE CICC , pp. 89-92
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  • 5
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    • DOI 10.1109/CICC.2007.4405683, 4405683, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC
    • J. Chen, Y.P. Xu, "A 94dB SFDR 78dB DR 2.2MHz BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC," in Proc. IEEE CICC, Sept. 2007, pp. 69-72. (Pubitemid 351276935)
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  • 9
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.