A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 89-92

  Choi, Moo Yeol ^a   Lee, Sung No ^a   You, Seung Bin ^a   Yeum, Wang Seup ^a   Park, Ho Jin ^a   Kim, Jae Whui ^a   Lee, Hae Seung ^b  

^a SAMSUNG Electronics   (South Korea)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK JITTER; CMOS PROCESSES; CONTINUOUS TIMES; DELTA SIGMAS; DIE AREAS; POST INTEGRATIONS; TIME CONSTANT VARIATIONS;

ACOUSTIC INTENSITY; CONTINUOUS TIME SYSTEMS; DELTA SIGMA MODULATION; INTEGRATION; JITTER; MULTICARRIER MODULATION; NETWORKS (CIRCUITS); PULSE CIRCUITS; PULSE GENERATORS; SIGNAL GENERATORS; SIGNAL TO NOISE RATIO;

INTEGRATED CIRCUITS;

EID: 57849131826     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672028     Document Type: Conference Paper

References (9)

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