A compression-based area-efficient recovery architecture for nonvolatile processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1519-1524

  Wang, Yiqun ^a   Liu, Yongpan ^a   Liu, Yumeng ^a   Zhang, Daming ^a   Li, Shuangchen ^a   Sai, Baiko ^b   Chiang, Mei Fang ^b   Yang, Huazhong ^a  

^a TSINGHUA UNIVERSITY   (China)

^b ROHM CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENT; AREA OVERHEAD; AREA SAVINGS; EMERGING TOPICS; NON-VOLATILE; NONVOLATILE MATERIALS; POWER FAILURE; PROCESSOR DESIGN; REFERENCE VECTORS; RUN LENGTH; STANDBY POWER; STATE TABLES;

COMPACTION; DATA COMPRESSION; DESIGN; EXHIBITIONS; OPTIMIZATION; RECONFIGURABLE ARCHITECTURES; VECTORS;

PARALLEL PROCESSING SYSTEMS;

EID: 84862082787     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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