Surface-roughness-induced variability in nanowire InAs tunnel FETs

IEEE Electron Device Letters

Volumn 33, Issue 6, 2012, Pages 806-808

  Conzatti, F ^a   Pala, M G ^b   Esseni, D ^a  

^a UNIVERSITY OF UDINE   (Italy)

^b IMEP LAHC   (France)

Author keywords

Nanowires; surface roughness; tunnel FET; variability

Indexed keywords

BANDBENDING; BUILT-IN POTENTIAL; COMPARATIVE STUDIES; DEPLETION REGION; GATE BIAS; INAS; LOW SUPPLY VOLTAGES; MOSFETS; NON-EQUILIBRIUM GREEN'S FUNCTION FORMALISM; SOURCE JUNCTIONS; STRAINED-SILICON; SUBBANDS; SUBTHRESHOLD; TUNNEL-FET; VARIABILITY;

INDIUM ARSENIDE; MOSFET DEVICES; NANOWIRES;

SURFACE ROUGHNESS;

EID: 84861687836     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2012.2192091     Document Type: Article

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