Overview: Continuous evolution on double-patterning process

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 8325, Issue , 2012, Pages

  Yaegashi, Hidetami ^a   Oyama, Kenichi ^a   Hara, Arisa ^a   Natori, Sakurako ^a   Yamauchi, Shohei ^a  

^a TOKYO ELECTRON LTD   (Japan)

Author keywords

11 nm node; Double patterning; Pitch doubling; Pitch quadrupling; Pitch tripling; SADP; SAQP

Indexed keywords

11 NM NODE; DOUBLE PATTERNING; PITCH-DOUBLING; PITCH-QUADRUPLING; PITCH-TRIPLING; SADP; SAQP;

ATOMIC LAYER DEPOSITION; LOGIC DEVICES; SILICA;

LITHOGRAPHY;

EID: 84861050066     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.915695     Document Type: Conference Paper

References (7)

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2. H. Yaegashi, et al., "Novel approaches to implement the self-aligned spacer DP process Toward 11- nm Nodes and Beyond, " proc. of SPIE 7972-10 (2011).
3. Michael C. Smayling, et al., "Low k1 logic design using gridded design rules" proc. of SPIE 6925 (2008).
4. V. Axelrad, et al., "Optical Lithography Applied to 20nm CMOS Logic and SRAM" proc. of SPIE 7973 (2011).
5. Carlos Fonseca, et al., "Advances and challenges in dual-tone development process optimization" proc. of SPIE 7274 (2009).
6. K. Oyama, et al., "The enhanced photoresist shrink process technique toward 22nm node" proc. of SPIE 7972 (2011).
7. H. Yaegashi et al., "Sustainability of Double Patterning process for Lithographic scaling" International Symposia on Lithography Extensions (2011).