Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7972, Issue , 2011, Pages

  Yaegashi, Hidetami ^a   Oyama, Kenichi ^a   Yabe, Kazuo ^a   Yamauchi, Shohei ^a   Hara, Arisa ^a   Natori, Sakurako ^a  

^a TOKYO ELECTRON LTD   (Japan)

Author keywords

11nm; Double patterning; RDR; Restricted design rule; SADP; Spacer Cut; Spacer DP

Indexed keywords

11NM; DOUBLE PATTERNING; RDR; RESTRICTED DESIGN RULES; SADP; SPACER DP;

MASKS; SEMICONDUCTOR DEVICE MANUFACTURE;

FLASH MEMORY;

EID: 79955901659     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.878943     Document Type: Conference Paper

References (3)

1. H. Yaegashi et al., "Important challenges for line-width-roughness reduction" Proc. of SPIE 7273-146 (2009)
2. A. Hara et al., "Advanced self-aligned DP process development for 22-nm node and beyond" Proc. of SPIE 7639-79 (2010)
3. K. Oyama et al., "The important challenge to extend spacer DP process towards 22nm and beyond" Proc. of SPIE 7639-6 (2010)