Optical lithography applied to 20nm CMOS logic and SRAM

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7973, Issue , 2011, Pages

  Axelrad, V ^a   Smayling, M C ^b   Tsujita, K ^c   Takahashi, K ^c  

^a Sequoia Design Systems Inc   (United States)

^b Tela Innovations Inc   (United States)

^c CANON INC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

193-NM IMMERSION; 193-NM LITHOGRAPHY; CD ERRORS; CMOS LOGIC; CO-OPTIMIZATION; CRITICAL LAYER; DESIGN RULES; DOUBLE PATTERNING; IMMERSION TECHNOLOGY; INDUSTRY CONSENSUS; LAYOUT AREA; LOGIC CELLS; MULTIPLE EXPOSURE; NOVEL ALGORITHM; PROXIMITY CORRECTION; REGULAR DESIGNS; REGULAR PATTERNS; SIMULATION-BASED; SINGLE EXPOSURE; STANDARD CELL; TEST CASE; TEST DESIGNS;

ALGORITHMS; DESIGN; ELECTRIC BATTERIES; LOGIC CIRCUITS; LOGIC DEVICES; OPTIMIZATION; PHOTOLITHOGRAPHY; SCANNING;

STATIC RANDOM ACCESS STORAGE;

EID: 79959241863     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.879522     Document Type: Conference Paper

References (5)

1. V. Axelrad, M. Smayling, "16nm with 193nm Immersion Lithography and Double Exposure, " SPIE, 2010.
2. K. Tsujita, K. Mikami, J. Ishii, T. Arai, K. Takahashi, "Lithography and layout co-optimization beyond conventional OPC concept, " SPIE, 2010.
3. M. Smayling, V. Axelrad, "Simulation-Based Lithography Optimization for Logic Circuits at 22nm and below, " SISPAD, 2009.
4. M. Smayling, V. Axelrad, "32nm and below Logic Patterning using Optimized Illumination and Double Patterning, " SPIE, 2009.
5. Y. Borodovsky, "Lithography 2009: Overview of Opportunities, " Semicon West, 2009.