A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 338-339

  Teh, Chen Kong ^a   Fujita, Tetsuya ^a   Hara, Hiroyuki ^a   Hamada, Mototsugu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; ENERGY EFFICIENCY; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

ADAPTIVE COUPLING; DESIGN AND TESTS; LOW POWER TECHNIQUES; LOW-POWER FLIP-FLOP; PROCESS VARIATION; TIMING PARAMETERS; TRANSISTOR COUNT; TRANSMISSION GATE;

FLIP FLOP CIRCUITS;

EID: 79955716216     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746344     Document Type: Conference Paper

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