A very low power and high throughput AES processor

14th International Conference on Computer and Information Technology, ICCIT 2011

Volumn , Issue , 2011, Pages 339-343

  Hossain, Fakir Sharif ^a   Ali, Md Liakot ^b   Al Abedin Syed, Musadek Anwarul ^a  

^a INTERNATIONAL ISLAMIC UNIVERSITY CHITTAGONG   (Bangladesh)

^b BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY   (Bangladesh)

Author keywords

AES Algorithm; FPGA; Low Power; PPP Analyzer Tool; Throughput

Indexed keywords

AES ALGORITHMS; COMPUTING DEVICES; DESIGN CONSIDERATIONS; HIGH THROUGHPUT; LOW POWER; LOW-POWER CONSUMPTION; NETWORK APPLICATIONS; POWER ANALYSIS; POWER ANALYZERS; POWER ESTIMATIONS; POWER PLAY; QUARTUS II; SECURITY FEATURES; SMART CARD READERS; STATIC AND DYNAMIC; SYSTEM INTEGRATION;

ALGORITHMS; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INFORMATION TECHNOLOGY; THROUGHPUT;

CRYPTOGRAPHY;

EID: 84859958613     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCITechn.2011.6164810     Document Type: Conference Paper

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