Polymer filling of silicon trenches for 3-D through silicon vias applications

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 6, 2011, Pages 825-832

  Duval, Fabrice F C ^a   Okoro, Chukwudi ^a   Civale, Yann ^a   Soussan, Philippe ^a   Beyne, Eric ^a  

^a IMEC   (Belgium)

Author keywords

3 D packaging; filling; finite element modeling; polymers; spin on dielectric

Indexed keywords

3D PACKAGING; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; CURE TEMPERATURE; DEEP TRENCH ISOLATION; EMERGING TECHNOLOGIES; FINITE ELEMENT MODELING; MECHANICAL ACTION; MULTIPLE DEVICES; POLYMER FILLING; PRE-WETTING; SILICON TRENCH; SPIN-ON DIELECTRICS; THROUGH SILICON VIAS; VERTICAL STACKING; WAFER LEVEL PACKAGING; WAFER SURFACE; WETTING PROPERTY;

COATINGS; CONTACT ANGLE; DELAMINATION; ELECTRONICS PACKAGING; FILLED POLYMERS; FILLING; MECHANICAL PROPERTIES; POLYMERS; SILICON WAFERS; WETTING;

THREE DIMENSIONAL;

EID: 84859798579     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2114885     Document Type: Article

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