3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques

Microelectronics Journal

Volumn 43, Issue 6, 2012, Pages 423-432

  Frantz, Felipe ^a   Labrak, Lioua ^a   Oconnor, Ian ^a  

^a ECOLE CENTRALE DE LYON   (France)

Author keywords

3D IC; Floorplanning; Multi objective optimization; Thermal; TSV

Indexed keywords

3-D INTEGRATION; 3D MOVE; CHIP ARCHITECTURE; COMPUTATION TIME; FLOOR-PLANNING; FLOORPLAN ALGORITHMS; HETEROGENEOUS INTEGRATION; MANAGEMENT TECHNIQUES; MULTI OBJECTIVE OPTIMIZATIONS (MOO); PEAK TEMPERATURES; PERFORMANCE IMPROVEMENTS; POWER CONSUMPTION REDUCTION; SOLUTION QUALITY; TEMPERATURE PEAKS; THERMAL; THERMAL DISTRIBUTIONS; TSV; WIRE LENGTH;

ALGORITHMS; INTEGRATION; MULTIOBJECTIVE OPTIMIZATION;

THREE DIMENSIONAL;

EID: 84859748416     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2012.03.005     Document Type: Article

References (25)

1. J.W. Joyner, R. Venkatesan, P. Zarkesh-Ha, J.A. Davis, and J.D. Meindl Impact of three-dimensional architectures on interconnects in gigascale integration IEEE Trans. Very Large Scale Integr. VLSI Syst. 9 6 2001 922 928
2. A. Rahman, and R. Reif System-level performance evaluation of three-dimensional integrated circuits, IEEE Trans. Very Large Scale Integr. VLSI Syst. 8 6 2000 671 678
3. W. Davis, E. Oh, A. Sule, and P. Franzon Application exploration for 3-D integrated circuits: TCAM, FIFO, and FFT case studies, IEEE Trans. Very Large Scale Integr. VLSI Syst. 17 4 2009 496 506
4. B. Aull, J. Burns, C. Chen, B. Felton, H. Hanson, C. Keast, J. Knecht, A. Loomis, M. Renzi, A. Soares, V. Suntharalingam, K. Warner, D. Wolfson, D. Yost, and D. Young, Laser radar imager based on 3d integration of Geiger-mode avalanche photodiodes with two soi timing circuit layers, in ISSCC, 2006, pp. 1179-1188.
5. V. Pavlidis, and E. Friedman Interconnect-based design methodologies for three-dimensional integrated circuits Proc. IEEE 97 1 2009 123 140
6. E.J. Marinissen, Testing TSVv-based three-dimensional stacked ICs, in DATE, 2010, pp. 1689-1694.
7. E.-K. Kim, and J. Sung Yield challenges in wafer stacking technology Microelectron. Reliab. 48 2008 112 1105
8. W. Huang, M. Stan, S. Gurumurthi, R. Ribando, and K. Skadron, Interaction of scaling trends in processor architecture and cooling,in SEMI-THERM, feb. 2010, pp. 198-204.
9. M. Sridhar, A. Raj, A. Vincenzi, M. Ruggiero, T. Brunschwiler, and D.Atienza Alonso, 3d-ICE: Fast compact transient thermal modelling for 3D-ICs with inter-tier liquid cooling, in Proceedings of the 2010 International Conference on Computer-Aided Design (ICCAD 2010), vol. 1, no. 1. New York: ACM and IEEE Press, 2010, pp. 1-8.
10. H. Yu, Y. Shi, L. He, and T. Karnik W. Islped, M.R. Nebel, A. Stan, J. Raghunathan, Henkel D. Marculescu, Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power 2006 ACM 156 161
11. B. Goplen, and S. Sapatnekar Placement of thermal vias in 3D ICs using various thermal objectives IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 4 2006 692 709
12. Y. Ma, D. Chong, C. Wang, and A. Sun, Development of ball grid array packages with improved thermal performance, in Proc. EPTC'05, Vol. 2, dec. 2005, p. 6 pp.
13. B. Agostini, M. Fabbri, J.E. Park, L. Wojtan, and J.R. Thome State-of-the-art of high heat flux cooling technologies Heat Transfer Eng. 28 4 2007 258 281
14. P. Zhou, Y. Ma, Z. Li, R.P. Dick, L. Shang, H. Zhou, X. Hong, and Q. Zhou 3D-STAF: scalable temperature and leakage aware oorplanning for three-dimensional integrated circuits G.G.E. ICCAD, Gielen IEEE 2007 590 597
15. J. Cong, J. Wei, and Y. Zhang, A thermal-driven oorplanning algorithm for 3D ICs, in ICCAD. IEEE Computer Society/ACM, 2004, pp. 306-313
16. L. Xiao, S. Sinha, J. Xu, and E. Young, Fixed-outline thermal-aware 3D oorplanning, in ASP-DAC, Jan. 2010, pp. 561-567.
17. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani VLSI module placement based on rectangle-packing by the sequence-pair IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 12 1996 1518 1524
18. H.H. Chan, S.N. Adya, and I.L. Markov, Are oorplan representations important in digital design, in In Proc. ISPD'05. ACM, 2005, pp. 129-136.
19. H. Cohn, and M. Fielding Simulated annealing: searching for an optimal temperature schedule SIAM J. Optim. 1999 779 802
20. S. Adya, and I. Markov Fixed-outline oorplanning: enabling hierarchical design IEEE Trans. Very Large Scale Integr. VLSI Syst. 11 6 2003 1120 1135
21. K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, Temperature-aware microarchitecture, in Proc. 30th International Symposium on Computer Architecture, June 2003, pp. 2-13, http://lava.cs. virginia.edu/HotSpot/documentation.htm.
22. MATLAB genetic algorithm toolbox - users guide.
23. International Technology Roadmap for Semiconductors 2009.
24. P. Wilkerson, M. Furmanczyk, and M. Turowski, Compact thermal modeling analysis for 3D integrated circuits, 11th International Conference Mixed Design of Integrated Circuits and Systems, June 2004.
25. [Online]. Available: http://cadlab.cs.ucla.edu/three-d/3dic.html