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Volumn 4, Issue 3, 2011, Pages

Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods

Author keywords

Integer linear programming; Iterative methods

Indexed keywords

BANDED MATRICES; GENERAL-PURPOSE PROCESSORS; HARDWARE DESIGN; INTEGER LINEAR PROGRAMMING; MATRIX VECTOR MULTIPLICATION; MEMORY BANDWIDTHS; ON CHIP MEMORY; PARALLELIZATIONS; PERFORMANCE GAIN; PERFORMANCE IMPROVEMENTS; SYSTEM OF LINEAR EQUATIONS;

EID: 84858198125     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/2000832.2000834     Document Type: Article
Times cited : (12)

References (19)
  • 6
    • 0004236492 scopus 로고    scopus 로고
    • 3rd Ed. Johns Hopkins University Press, Baltimore, MD
    • GOLUB, G. H. AND LOAN, C. F. V. 1996. Matrix Computations, 3rd Ed. Johns Hopkins University Press, Baltimore, MD.
    • (1996) Matrix Computations
    • Golub, G.H.1    Loan, C.F.V.2
  • 8
    • 12444294469 scopus 로고
    • Time complexity of a parallel conjugate gradient solver for light scattering simulations: Theory and SPMD implementation
    • HOEKSTRA, A. G., SLOOT, P.,HOFFMANN, W., AND HERTZBERGER, L. 1992. Time complexity of a parallel conjugate gradient solver for light scattering simulations: Theory and spmd implementation. Tech. rep., University of Amsterdam.
    • (1992) Tech. Rep., University of Amsterdam
    • Hoekstra, A.G.1    Sloot, P.2    Hoffmann, W.3    Hertzberger, L.4
  • 9
    • 71749094842 scopus 로고    scopus 로고
    • ILOG, INC. 2009. Solver cplex. http://www.ilog.fr/products/cplex/.
    • (2009) Solver CPLEX
  • 15
    • 60649092766 scopus 로고    scopus 로고
    • XILINX. 2010. Virtex-5 FPGA User Guide. http://www.xilinx.com/support/ documentation/user-guides/ug190.pdf.
    • (2010) Virtex-5 FPGA User Guide
  • 17
    • 34648814129 scopus 로고    scopus 로고
    • High-Performance reduction circuits using deeply pipelined operators on FPGAs
    • ZHUO, L.,MORRIS, G. R., AND PRASANNA, V. K. 2007. High-Performance reduction circuits using deeply pipelined operators on FPGAs. IEEE Trans. Parall. Distrib. Syst. 18, 10, 1377-1392.
    • (2007) IEEE Trans. Parall. Distrib. Syst. , vol.18 , Issue.10 , pp. 1377-1392
    • Zhuo, L.1    Morris, G.R.2    Prasanna, V.K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.