An FPGA-based implementation of the minres algorithm

Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2008, Pages 379-384

  Boland, David ^a   Constantinides, George A ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CONTINUOUS IMPROVEMENTS; FLOATING-POINT; HARDWARE IMPLEMENTATIONS; PARALLELISATION; PRECISION FLOATING POINTS; SOFTWARE IMPLEMENTATIONS; SUSTAINED PERFORMANCES; SYSTEM OF LINEAR EQUATIONS; TIME CONSUMING;

BOOLEAN FUNCTIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LINEAR EQUATIONS;

ALGORITHMS;

EID: 54949089314     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2008.4629967     Document Type: Conference Paper

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